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Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0344402 (1999-06-25)
발명자 / 주소
  • Liu Chung-Shi,TWX
  • Yu Chen-Hua,TWX
  • Bao Tien-I,TWX
  • Jang Syun-Ming,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 77  인용 특허 : 17

초록

Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conduc

대표청구항

[ What is claimed is as follows:] [1.] A method of forming a device on a surface of a conductive substrate comprising:forming a dielectric layer over said surface, said dielectric layer having a top level;forming a trench with sidewalls through said dielectric layer to expose a portion of said surfa

이 특허에 인용된 특허 (17)

  1. Aboelfotoh Mohamed O. (Poughkeepsie NY) Brady Michael J. (Manor ; Brewster NY) Krusin-Elbaum Lia (Dobbs Ferry NY), Compound with room temperature electrical resistivity comparable to that of elemental copper.
  2. Liu Chung-Shi,TWX ; Chang Chung-Long,TWX ; Yu Chen-Hua,TWX, Copper chemical-mechanical-polishing (CMP) dishing.
  3. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  4. Joshi Rajiv Vasant ; Tejwani Manu Jamnadas ; Srikrishnan Kris Venkatraman, High aspect ratio low resistivity lines/vias with a tungsten-germanium alloy hard cap.
  5. Cronin John Edward, Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same.
  6. Batra Shubneesh ; Sandhu Gurtej, Low temperature reflow method for filling high aspect ratio contacts.
  7. Filipiak Stanley M. (Pflugerville TX) Gelatos Avgerinos (Austin TX), Method for capping copper in semiconductor devices.
  8. Roy Sudipto Ranendra,SGX, Method for forming copper damascene structures by using a dual CMP barrier layer.
  9. Jain Ajay, Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer.
  10. Joshi Rajiv V. (Yorktown Heights NY) Tejwani Manu J. (Yorktown Heights NY) Srikrishnan Kris V. (Wappingers Falls NY), Method of making corrosion resistant, low resistivity copper for interconnect metal lines.
  11. Chan Lap ; Zheng Jia Zhen,SGX, Method of manufacturing copper interconnect with top barrier layer.
  12. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  13. Misawa Nobuhiro (Kawasaki JPX), Process for fabricating integrated circuit devices.
  14. Jain Ajay, Process for forming a semiconductor device.
  15. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
  16. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias.
  17. Ericson ; Harry ; Fredriksson ; Carl Otto, Solutions for chemically polishing surfaces of copper and its alloys.

이 특허를 인용한 특허 (77)

  1. Robert T. Rozbicki, Anti-agglomeration of copper seed layers in integrated circuit metalization.
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  3. Klawuhn,Erich R.; Rozbicki,Robert; Dixit,Girish A., Apparatus and methods for deposition and/or etch selectivity.
  4. Pradhan, Anshu A.; Rozbicki, Robert, Atomic layer profiling of diffusion barrier and metal seed layers.
  5. Pradhan, Anshu A.; Rozbicki, Robert, Atomic layer profiling of diffusion barrier and metal seed layers.
  6. Maes, Jan Willem; Knaepen, Werner; Gronheid, Roel; Singh, Arjun, Combined anneal and selective deposition process.
  7. Shaviv, Roey; Gopinath, Sanjay; Holverson, Peter; Pradhan, Anshu A., Conformal films on semiconductor substrates.
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  9. Weidman, Timothy W.; Wijekoon, Kapila P.; Zhu, Zhize; Gelatos, Avgerinos V. (Jerry); Khandelwal, Amit; Shanmugasundram, Arulkumar; Yang, Michael X.; Mei, Fang; Moghadam, Farhad K., Contact metallization scheme using a barrier layer over a silicide layer.
  10. Luo, Qian; Sundarrajan, Arvind; Chung, Hua; Tang, Xianmin; Yu, Jick M.; Narasimhan, Murali K., Cu surface plasma treatment to improve gapfill window.
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  12. Dulkin, Alexander; Vijayendran, Anil; Yu, Tom; Juliano, Daniel R., Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer.
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  16. Agarwal, Vishnu Kumar, Encapsulated conductive pillar.
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  20. Sukharev, Valeriy; Catabay, Wilbur G.; Lu, Hongqiang, Interconnect integration.
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  27. Chang, Hui-Lin; Tsai, Hung Chun; Lu, Yung-Cheng; Jang, Syun-Ming, Interconnect structures for semiconductor devices.
  28. Pfuetzner, Ronny; Heinrich, Jens, Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material.
  29. Pradhan, Anshu A.; Hayden, Douglas B.; Kinder, Ronald L.; Dulkin, Alexander, Method and apparatus for increasing local plasma density in magnetically confined plasma.
  30. Danek, Michal; Rozbicki, Robert, Method for depositing a diffusion barrier for copper interconnect applications.
  31. Shue, Shau-Lin; Liang, Mong-Song, Method for forming a self-passivated copper interconnect structure.
  32. John A. Iacoponi ; Paul R. Besser ; Frederick N. Hause ; Frank Mauersberger DE; Errol Todd Ryan ; William S. Brennan ; Peter J. Beckage, Method for forming copper interconnects.
  33. McGahay, Vincent J.; Ivers, Thomas H.; Liu, Joyce C.; Nye, III, Henry A., Method for improving adhesion to copper.
  34. West,Jeffrey A.; Barth,Michael D.; Zuhoski,Steven P., Method for improving reliability of copper interconnects.
  35. Carbonell, Laure Elisa; Peter, Antony Premkumar; Schaekers, Marc; Van Elshocht, Sven; Tokei, Zsolt, Method for manufacturing germamde interconnect structures and corresponding interconnect structures.
  36. Arne W. Ballantine ; Edward C. Cooney, III ; George A. Dunbar, III ; Cheryl G. Faltermeier ; Jeffrey D. Gilbert ; Ronald D. Goldblatt ; Nancy A. Greco ; Stephen E. Greco ; Frank V. Liucci ; , Method of annealing copper metallurgy.
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  40. Hohage, Joerg; Kahlert, Volker; Ruelke, Hartmut; Mayer, Ulrich, Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment.
  41. Agarwal, Vishnu Kumar, Method of forming an encapsulated conductive pillar.
  42. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Method of increasing the stability of a copper to copper interconnection process and structure manufactured thereby.
  43. Merchant Sailesh Mansinh ; Misra Sudhanshu ; Moller William Michael ; Roy Pradip Kumar, Method of making a semiconductor with copper passivating film.
  44. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Method of preparing passivated copper line and device manufactured thereby.
  45. Chopra, Dinesh, Method of reducing oxidation of metal structures by selectively implanting ions through a mask positioned above and not in contact with the substrate.
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  48. Chen-Hua Yu TW; Mong-Song Liang TW, Method to form copper interconnects.
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  50. Rozbicki, Robert, Methods and apparatus for resputtering process that improves barrier coverage.
  51. Alford, Terry L.; Dhar, Aritra, Microwave-annealed indium gallium zinc oxide films and methods of making the same.
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  69. Juliano, Daniel R., Selective resputtering of metal seed layers.
  70. Shue,Shau Lin; Liang,Mong Song, Self-passivated copper interconnect structure.
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