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Heat transfer configuration for a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/34
  • H01L-023/48
출원번호 US-0824844 (1997-03-26)
우선권정보 JP-0072592 (1996-03-27)
발명자 / 주소
  • Yano Keiichi,JPX
  • Asai Hironori,JPX
출원인 / 주소
  • Kabushiki Kaisha Toshiba, JPX
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
인용정보 피인용 횟수 : 40  인용 특허 : 21

초록 ▼

Disclosed is a semiconductor package having: a semiconductor chip; a package substrate; a wire connected to the semiconductor chip; and an electric connection member formed on the package substrate to electrically connect the wire to a printed board when the package substrate is mounted on the print

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor package comprising:a semiconductor chip;a package substrate composed of ceramic on which the semiconductor chip is mounted;a wire formed on the package substrate and connected to the semiconductor chip; andan electric connection member formed on the packag

이 특허에 인용된 특허 (21)

  1. Banerji Kingshuk (Plantation FL) Nounou Fadia (Plantation FL) Mullen ; III William B. (Boca Raton FL), Backplane grounding for flip-chip integrated circuit.
    상세보기
  2. Ho Tony H. (Hsin-Chu TWX), Ball grid array having reduced mechanical stress.
    상세보기
  3. Selna Erich (Mountain View CA), Ball grid array package for a integrated circuit.
    상세보기
  4. Shim Il Kwon,KRX ; Heo Young Wook,KRX, Ball grid array semiconductor package with improved heat dissipation and dehumidification effect.
    상세보기
  5. Belopolsky Yakov (Hockessin DE), Electronic assembly with optimum heat dissipation.
    상세보기
  6. Koiwa Kaoru,JPX ; Yamakawa Koji ; Iyogi Kiyoshi,JPX ; Yasumoto Takaaki,JPX ; Iwase Nobuo,JPX, Electronic component and electronic component connecting structure.
    상세보기
  7. Iwasaki Ken,JPX, Electronic device and semiconductor package.
    상세보기
  8. Komatsu Michiyasu (Yokohama JPX) Sato Yoshitoshi (Yokohama JPX) Shinosawa Katsuhiro (Kawasaki JPX) Yamaga Mineyuki (Yomohama JPX), High thermal conductive silicon nitride structural member, semiconductor package, heater and thermal head.
    상세보기
  9. Newman Keith G. (Sunnyvale CA), Integrated circuit package lid.
    상세보기
  10. Lin Paul T. (Austin TX), Leaded semiconductor device having accessible power supply pad terminals.
    상세보기
  11. Haji Hiroshi,JPX ; Sakemi Shoji,JPX, Method of manufacturing an electronic component.
    상세보기
  12. Miyagi Takeshi (Fujisawa JPX) Matsumoto Kazuhiro (Yokohama JPX) Sasaki Tomiya (Yokohama JPX) Iwasaki Hideo (Kawasaki JPX) Hisano Katsumi (Yokohama JPX), Multi-layer substrate.
    상세보기
  13. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX), Overmolded semiconductor device having solder ball and edge lead connective structure.
    상세보기
  14. Chao Chien-Chi (Taipei TWX) Lin Ming-Hane (Chu-Pei TWX) Ho Ted C. (Hsinchu TWX), Packaging assembly with consolidated common voltage connections for integrated circuits.
    상세보기
  15. Pastore John R. (Leander TX) Nomi Victor K. (Round Rock TX) Wilson Howard P. (Austin TX), Pad array semiconductor device with thermal conductor and process for making the same.
    상세보기
  16. Wilson James W. (Vestal NY), Semiconductor chip package with enhanced thermal conductivity.
    상세보기
  17. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX) Wilson Howard P. (Austin TX), Semiconductor device having a pad array carrier package.
    상세보기
  18. Higgins ; III Leo M. (Austin TX), Semiconductor device having compliant columnar electrical connections.
    상세보기
  19. Yano Keiichi,JPX ; Asai Hironori,JPX ; Koiwa Kaoru,JPX ; Iwase Nobuo,JPX, Semiconductor package and semiconductor mounting part.
    상세보기
  20. Ommen Denise M. (Phoenix AZ) Tsai Chi-Taou (Chandler AZ) Baird John (Scottsdale AZ), Semiconductor package capable of spreading heat.
    상세보기
  21. Endo Mitsuyoshi (25-23-3F Higashikashiwagaya 4-chome Ebina-shi ; Kanagawa-ken JPX) Asai Hironori (2469-6-625 Nagatsudacho ; Midori-ku Yokohama-shi ; Kanagawa-ken JPX) Yano Keiichi (11-301 ; Daishihon, Semiconductor package having an aluminum nitride substrate.
    상세보기

이 특허를 인용한 특허 (40)

  1. Mulligan, Anthony C.; Rigali, Mark J.; Sutaria, Manish P.; Popovich, Dragan; Halloran, Joseph P.; Fulcher, Michael L.; Cook, Randy C., Aligned composite structures for mitigation of impact damage and resistance to wear in dynamic environments.
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  2. Mulligan, Anthony C.; Rigali, Mark J.; Sutaria, Manish P.; Popovich, Dragan; Halloran, Joseph P.; Fulcher, Michael L.; Cook, Randy C., Aligned composite structures for mitigation of impact damage and resistance to wear in dynamic environments.
    상세보기
  3. Andry, Paul S.; Cotte, John M.; Knickerbocker, John U.; Tsang, Cornelia K., Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers.
    상세보기
  4. Andry, Paul S.; Cotte, John M.; Knickerbocker, John U.; Tsang, Cornelia K., Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers.
    상세보기
  5. Lin Shih-Hao,TWX, Ball grid array package with conductive leads.
    상세보기
  6. Tzong-Da Ho TW; Chih-Chin Liao TW; Chien-Te Chen TW, Ball grid array package with interdigitated power ring and ground ring.
    상세보기
  7. Shivkumar, Bharat; Kinzer, Daniel M.; Munoz, Jorge, Chip-scale package.
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  8. Shivkumar,Bharat; Kinzer,Daniel M.; Munoz,Jorge, Chip-scale package.
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  9. Sutaria, Manish P.; Rigali, Mark J.; Cipriani, Ronald A.; Artz, Gregory J.; Mulligan, Anthony C., Consolidation and densification methods for fibrous monolith processing.
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  10. Sutaria,Manish P.; Rigali,Mark J.; Cipriani,Ronald A.; Artz,Gregory J.; Mulligan,Anthony C., Consolidation and densification methods for fibrous monolith processing.
    상세보기
  11. Neftin, Shimon; Mirsky, Uri, Device for electronic packaging, pin jig fixture.
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  12. Soga, Tasao; Shimokawa, Hanae; Nakatsuka, Tetsuya; Nakamura, Masato; Fujita, Yuji; Ishida, Toshiharu; Okamoto, Masahide; Serizawa, Koji; Hachiya, Toshihiro; Mukuno, Hideki, Electron device and semiconductor device.
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  13. Ichihara, Yasuhiro; Kogure, Seiji; Iimura, Hiroshi; Arase, Fumio, Electronic component package, printed circuit board, and method of inspecting the printed circuit board.
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  14. Yasuhiro Ichihara JP; Seiji Kogure JP; Hiroshi Iimura JP; Fumio Arase JP, Electronic component package, printing circuit board, and method of inspecting the printed circuit board.
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  15. Soga, Tasao; Shimokawa, Hanae; Nakatsuka, Tetsuya; Nakamura, Masato; Fujita, Yuji; Ishida, Toshiharu; Okamoto, Masahide; Serizawa, Koji; Hachiya, Toshihiro; Mukuno, Hideki, Electronic device.
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  16. Racz, Livia M.; Tepolt, Gary B.; Thompson, Jeffrey C.; Langdo, Thomas A.; Mueller, Andrew J., Electronic modules.
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  17. Racz, Livia M.; Tepolt, Gary B.; Thompson, Jeffrey C.; Langdo, Thomas A.; Mueller, Andrew J., Electronic modules and methods for forming the same.
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  18. Coullomb, Alexandre, Integrated circuit chip comprising electronic device and electronic system.
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  19. Utagikar, Ajit; Chong, Num-Kwee, Integrated circuit package with an IC chip and pads that dissipate heat away from the chip.
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  20. Racz, Livia M.; Tepolt, Gary B.; Thompson, Jeffrey C.; Langdo, Thomas A.; Mueller, Andrew J., Interposers, electronic modules, and methods for forming the same.
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  21. Liu Wen-Chun,TWX ; Lai Chien-Hung,TWX, Lead frame type semiconductor package.
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  22. Celaya,Phillip C.; Donley,James S.; St. Germain,Stephen C., Lead-free integrated circuit package structure.
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  23. Yano, Keiichi, Light emitting device, lighting equipment or liquid crystal display device using such light emitting device.
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  24. Celaya, Phillip C.; Donley, James S.; St. Germain, Stephen C., Method of making a lead-free integrated circuit package.
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  25. Usami,Mitsuo, Method of manufacturing an electronic device.
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  26. Usami,Mitsuo, Method of manufacturing an electronic device.
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  27. Basker, Veeraraghaven S.; Cotte, John Michael; Deligianni, Hariklia; Knickerbocker, John Ulrich; Kwietniak, Keith T., Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density.
    상세보기
  28. Mulligan, Anthony C.; Rigali, Mark J.; Sutaria, Manish P.; Artz, Gregory J.; Gafner, Felix H.; Vaidyanathan, K. Ranji, Methods for preparation of three-dimensional bodies.
    상세보기
  29. Mulligan,Anthony C.; Rigali,Mark J.; Sutaria,Manish P.; Artz,Gregory J.; Gafner,Felix H.; Vaidyanathan,K. Ranji, Methods for preparation of three-dimensional bodies.
    상세보기
  30. Wu, Albert; Chen, Roawen; Han, Chung Chyung (Justin); Liou, Shiann-Ming; Wei, Chien-Chuan; Chang, Runzi; Wu, Scott; Cheng, Chuan-Cheng, Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate.
    상세보기
  31. Andoh,Seiji, Package structure for a semiconductor device.
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  32. Andoh, Seiji, Package structure for a semiconductor device incorporating enhanced solder bump structure.
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  33. Shimizu, Yoshiaki; Yamada, Yuichiro; Fukuda, Toshiyuki, Semiconductor device and method of manufacturing the same.
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  34. Shimizu, Yoshiaki; Yamada, Yuichiro; Fukuda, Toshiyuki, Semiconductor device and method of manufacturing the same.
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  35. Iwazaki, Yoshihide; Ishio, Toshiya; Nakanishi, Hiroyuki; Mori, Katsunobu, Semiconductor device in which a plurality of electronic components are combined with each other.
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  36. Kawahara, Toshimi; Suwa, Mamoru; Onodera, Masanori; Monma, Syuichi; Nakaseko, Shinya; Hozumi, Takashi, Semiconductor device including stud bumps as external connection terminals.
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  37. Yang, Chia-Ming; Liang, Shu-Fen; Chou, Shu-Min, Semiconductor device with heat-dissipating capability.
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  38. Dhong Sang Hoo ; Hofstee Harm Peter ; Shapiro Michael Jay, Silicon packaging with through wafer interconnects.
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  39. Shimon Neftin IL; Uri Mirsky IL, Substrate for electronic packaging, pin jig fixture.
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  40. Nath, Jayesh; Shen, Ying, Systems and methods for improved chip device performance.
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