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Electrophoretic coating methodology to improve internal package delamination and wire bond reliability

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0986087 (1997-12-08)
발명자 / 주소
  • Hatchard Colin D.
  • Blish
  • II Richard C.
출원인 / 주소
  • Advanced Micro Devices
대리인 / 주소
    LaRiviere, Grubman & Payne, LLP
인용정보 피인용 횟수 : 28  인용 특허 : 4

초록

Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The principles of the present invention contemplate electrostatically depositing an exceptionally uniform coating on electronic components, especially

대표청구항

[ We claim:] [1.] A method for packaging an electronic, the device including at least one electrical lead, the method comprising the steps of:electrostatically applying a coating material to the electronic device and at least a portion of the lead, wherein the step of electrostatically applying a co

이 특허에 인용된 특허 (4)

  1. Yamazaki Shunpei (Tokyo JPX) Takemura Yasuhiko (Kanagawa JPX), Electronic device and a manufacturing method for the same.
  2. Zechman John Harold (Endicott NY), Integrated circuit chip composite having a parylene coating.
  3. Aigoo Seiichiro (15-13 ; Negishi 3-chome Taito-Ku ; Tokyo 110 JPX), Method of manufacturing semiconductor device with plated bump.
  4. Yamazaki Shunpei (Tokyo JPX), Semiconductor device having a film-covered packaged component.

이 특허를 인용한 특허 (28)

  1. Malatkar, Pramod, Bumpless build-up layer package with pre-stacked microelectronic devices.
  2. Malatkar, Pramod, Bumpless build-up layer package with pre-stacked microelectronic devices.
  3. Malatkar, Pramod, Bumpless build-up layer package with pre-stacked microelectronic devices.
  4. Lo Verde, Domenico; Bruno, Giuseppe, Electric connection structure for electronic power devices, and method of connection.
  5. Hidaka,Akio; Murano,Yuichi, Electronic component.
  6. Hidaka,Akio; Murano,Yuichi, Electronic component.
  7. Kuo, Frank, Encapsulation method and leadframe for leadless semiconductor packages.
  8. Kuo,Frank, Encapsulation method for leadless semiconductor packages.
  9. Kuo, Frank, Encapsulation techniques for leadless semiconductor packages.
  10. Shen, Zheng John, High-temperature, wirebondless, injection-molded, ultra-compact hybrid power module.
  11. Fernandez Joseph, Method for reducing die cracking in integrated circuits.
  12. Lee, Charles-Wee-Ming; Strack, Helmut, Method of assembling a semiconductor device package.
  13. Blish ; II Richard C. ; Hatchard Colin ; Morgan Ian, Method to improve chip scale package electrostatic discharge performance and suppress marking artifacts.
  14. Mathew, Varughese; Chopin, Sheila F.; Higgins, III, Leo M., Mold compound compatibility test system and methods thereof.
  15. Hidaka,Akio; Murano,Yuuichi; Wakasugi,Shinichi; Fujimoto,Hidetsugu, Multilayer capacitor and mold capacitor.
  16. Miyaki Yoshinori,JPX ; Suzuki Hiromichi,JPX ; Suzuki Kazunari,JPX ; Nishita Takafumi,JPX ; Ito Fujio,JPX ; Tsubosaki Kunihiro,JPX ; Kameoka Akihiko,JPX ; Nishi Kunihiko,JPX, Plastic molded type semiconductor device and fabrication process thereof.
  17. Miyaki, Yoshinori; Suzuki, Hiromichi; Suzuki, Kazunari; Nishita, Takafumi; Ito, Fujio; Tsubosaki, Kunihiro; Kameoka, Akihiko; Nishi, Kunihiko, Plastic molded type semiconductor device and fabrication process thereof.
  18. Miyaki, Yoshinori; Suzuki, Hiromichi; Suzuki, Kazunari; Nishita, Takafumi; Ito, Fujio; Tsubosaki, Kunihiro; Kameoka, Akihiko; Nishi, Kunihiko, Plastic molded type semiconductor device and fabrication process thereof.
  19. Miyaki, Yoshinori; Suzuki, Hiromichi; Suzuki, Kazunari; Nishita, Takafumi; Ito, Fujio; Tsubosaki, Kunihiro; Kameoka, Akihiko; Nishi, Kunihiko, Plastic molded type semiconductor device and fabrication process thereof.
  20. Riedl, Edmund; Jordan, Steffen; Schilz, Christof Matthias; Wong, Fee Hoon, Semiconductor package and method of assembling a semiconductor package.
  21. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  22. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  23. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  24. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  25. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  26. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  27. Warren M. Farnworth, Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
  28. Hidaka Akio,JPX ; Hamazono Akito,JPX ; Sasaki Katsumi,JPX ; Ikebe Shoichi,JPX, Surface mount electronic component having electrodes suppressing the occurrence of migration.
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