초록 ▼

A field programmable gate array (FPGA) having an array of configurable logic blocks (CLBs) which can be partially reconfigured. Each column of CLBs is connected to a corresponding column select line, and each row of CLBs is connected to a corresponding row select line. A rectangular set of CLBs to b

A field programmable gate array (FPGA) having an array of configurable logic blocks (CLBs) which can be partially reconfigured. Each column of CLBs is connected to a corresponding column select line, and each row of CLBs is connected to a corresponding row select line. A rectangular set of CLBs to be reconfigured is selected, wherein the rectangular set of CLBs is defined by the intersection of one or more consecutive columns of CLBs and one or more consecutive rows of CLBs. Column select signals are asserted on the column select lines associated with the one or more consecutive columns of CLBs. Similarly, row select signals are asserted on the row select lines associated with the one or more consecutive rows of CLBs. CLBs which receive both an asserted column select signal and an asserted row select signal are enabled for reconfiguration.

대표청구항 ▼

[ What is claimed is:] [1.] A method for partially reconfiguring an array of configurable logic blocks (CLBs) arranged in a plurality of rows and columns, the method comprising the steps of:connecting each column of CLBs to a corresponding column select line;connecting each row of CLBs to a correspo

[ What is claimed is:] [1.] A method for partially reconfiguring an array of configurable logic blocks (CLBs) arranged in a plurality of rows and columns, the method comprising the steps of:connecting each column of CLBs to a corresponding column select line;connecting each row of CLBs to a corresponding row select line;selecting a rectangular set of CLBs to be reconfigured, wherein the rectangular set of CLBs is defined by the intersection of one or more consecutive columns of CLBs and one or more consecutive rows of CLBs;asserting column select signals on the column select lines associated with the one or more consecutive columns of CLBs;asserting row select signals on the row select lines associated with the one or more consecutive rows of CLBs; andenabling reconfiguration circuits within each CLB which receives both an asserted column select signal and an asserted row select signal; rein the step of asserting the column select signals further comprises the steps of:asserting a first column select signal on a first column select line;propagating the first column select signal to one or more consecutive column select lines; andgenerating a control signal for stopping the propagation of the first column select signal.