초록 ▼

A dynamically reconfigurable FPGA includes an array of tiles on a logic plane and a plurality of memory planes. Each tile has associated storage elements on each memory plane, called local memory. This local memory allows large amounts of data to pass from one FPGA configuration (memory plane) to an

A dynamically reconfigurable FPGA includes an array of tiles on a logic plane and a plurality of memory planes. Each tile has associated storage elements on each memory plane, called local memory. This local memory allows large amounts of data to pass from one FPGA configuration (memory plane) to another with no external memory access, thereby transferring data to/from the storage elements in the logic plane at very high speed. Typically, all the local memory can be simultaneously transferred to/from other memory planes in one cycle. Each FPGA configuration provides a virtual instruction. The present invention uses two different types of virtual instructions: computational and pattern manipulation instructions. Computational instructions perform some computation with data stored in some pre-defined local memory pattern. Pattern manipulation instructions move the local data into different memory locations to create the pattern required by the next instruction. A virtual computation may be accomplished by a sequence of instructions.

대표청구항 ▼

[ What is claimed is:] [1.] A method for computation in a programmable logic device (PLD), said PLD including a logic plane and a plurality of memory planes, said method comprising:storing configuration data and user data in said memory planes, said configuration data providing a configuration of sa

[ What is claimed is:] [1.] A method for computation in a programmable logic device (PLD), said PLD including a logic plane and a plurality of memory planes, said method comprising:storing configuration data and user data in said memory planes, said configuration data providing a configuration of said PLD, and said configuration of said PLD using said user data providing a single instruction in said computation; andsequentially reconfiguring said PLD in a series of configurations using said configuration data and user data, said series of configurations providing said computation,wherein each computation is comprised of computation steps, each computation step receiving input data, generating output data, and using programmable routing of said PLD to provide output data from one computation step as input data for another computation step.