초록 ▼

A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SR

A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector is provided such that when both read and write ports in the SRAM block access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block or the new data being written to the SRAM block.

대표청구항 ▼

[ What is claimed is:] [1.] A dual ported static random access memory block comprising:a write port having a plurality of write address inputs, a plurality of write data inputs, and a plurality of write enable inputs;a read port having a plurality of read address inputs, a plurality of read data inp

[ What is claimed is:] [1.] A dual ported static random access memory block comprising:a write port having a plurality of write address inputs, a plurality of write data inputs, and a plurality of write enable inputs;a read port having a plurality of read address inputs, a plurality of read data inputs, a plurality of read enable inputs, a plurality of read output enable control inputs, and a read output enable input; anda write enable circuit in said write port connected to said plurality of write enable inputs, said write enable circuit having a plurality of polarity select circuits, each of said polarity select circuits having an input connected to one of said write enable inputs and an output, and an AND gate having a plurality of inputs and an output, each of said plurality of inputs connected to a separate one of said outputs of said polarity select circuits.