초록 ▼

A method is disclosed for forming copper damascene interconnects without the attendant CMP (chemical-mechanical polishing) dishing problem that is encountered in the art. This is accomplished by first lining the inside walls of a dual damascene structure with a diffusion barrier layer, and then depo

A method is disclosed for forming copper damascene interconnects without the attendant CMP (chemical-mechanical polishing) dishing problem that is encountered in the art. This is accomplished by first lining the inside walls of a dual damascene structure with a diffusion barrier layer, and then depositing copper metal into the damascene structure. Secondly, as a key aspect of the invention, and before removing the excess copper either by conventional etching techniques-which is difficult for copper- or by conventional CMP- which causes dishing in grooves or trenches- an etch stop layer is deposited covering the copper layer. Portions of the etch stop layer is next removed from the high regions of the underlying copper by a quick first CMP so that other portions of the etch stop layer over the wider trenches/groove remain low and unaffected. The high regions now exposed are etched while the low regions protected by the etch-stop layer still remain unaffected. When the copper etching reaches a level below the level of the low regions, a global CMP is performed so that all of the excess copper is removed and the level of the copper especially over the wider trench areas reaches within very close proximity of the level of the insulation layer surrounding the copper damascene- and without dishing.

대표청구항 ▼

[ What is claimed is:] [1.] A method of using an etch-stop layer for chemical-mechanical polishing (CMP) of copper damascene comprising the steps of:providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon;forming a lower

[ What is claimed is:] [1.] A method of using an etch-stop layer for chemical-mechanical polishing (CMP) of copper damascene comprising the steps of:providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon;forming a lower level dielectric (LLD) layer over said substrate;forming a first etch-stop layer over said LLD layer;forming an upper level dielectric (ULD) layer over said first etch-stop layer;forming a first photoresist layer over said ULD layer;patterning said first photoresist layer with a hole pattern;etching through said hole pattern in said first photoresist layer into said ULD layer;etching further said hole pattern into said first etch-stop layer;removing said first photoresist layer from said substrate;forming a second photoresist layer over said substrate including said hole pattern;patterning said second photoresist layer with a conductive line groove pattern;etching through said conductive line groove in said second photoresist layer into said ULD layer until first etch-stop layer is reached;etching further and transferring said hole pattern from said ULD layer into said LLD layer until a lower level said substructure of said substrate is reached thus forming a composite groove/hole structure;removing said second photoresist layer;forming a barrier layer covering said substrate including the inside walls of said composite groove/hole structure;forming metal in said composite groove/hole structure;forming a second etch-stop layer over said substrate covering said metal;performing a first chemical-mechanical polishing of said substrate to remove said second etch-stop layer from higher regions and expose underlying said metal forming exposed regions while leaving said second etch-stop layer as a protective layer over lower regions on said substrate;etching said metal in said exposed regions; andperforming a second chemical-mechanical polishing for global planarization of said substrate.