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A bus architecture for use in a data communication system provides a communication path between processors and one or more external devices including (M+1) hierarchical processors. Each of the processors is categorized into one of N hierarchies with M and N being a positive integer larger than 1, re

A bus architecture for use in a data communication system provides a communication path between processors and one or more external devices including (M+1) hierarchical processors. Each of the processors is categorized into one of N hierarchies with M and N being a positive integer larger than 1, respectively, and N is smaller than (M+1). The bus architecture includes a bus having N buses, each of the buses coupled to one or more processors of a hierarchy and (N-1) linking means, and each of the linking means for coupling a bus of a hierarchy to a bus of a next hierarchy.

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[ What is claimed is:] [1.] A hierarchical bus architecture for use in a data communication system for providing a communication path between a plurality of processors and one or more external devices coupled to the system, said bus architecture comprising:a first bus;first, second and third nodes,

[ What is claimed is:] [1.] A hierarchical bus architecture for use in a data communication system for providing a communication path between a plurality of processors and one or more external devices coupled to the system, said bus architecture comprising:a first bus;first, second and third nodes, each directly connected to said first bus;a main processor belonging to a first hierarchy and connected to said first bus via said first node;at least one external device connected to said first bus via said second node;a second bus connected to said first bus via only said third node, wherein said second bus comprises redundant first and second data paths; anda plurality of peripheral processors belonging to a second hierarchy and connected to said second bus, wherein each of said peripheral processors is connected to both of said first and second data paths of said second bus and includes:a microprocessor;a first matching unit connected to said microprocessor and arranged to selectively connect said microprocessor to said first data paths; anda second matching unit connected to said microprocessor and arranged to selectively connect said microprocessor to said second data path,wherein said third node comprises first and second gateway nodes, each gateway node having a first and a second connection to respective said first and second data paths of said second bus, each gateway node also having a third connection to said first bus,wherein said each gateway node includes:first and second path matching units connected to corresponding said first and second data paths;a receive selection unit arranged to receive an input from each of said first and second path matching units, and further arranged to output a signal to said first bus; anda transmit control unit arranged to receive an input from said first bus, and further arranged to output a signal to both of said first and second path matching units.