초록 ▼

The invention also concerns a memory device having a plurality of memory banks and configurable logic units associated with the memory banks. An interconnect is provided to enable communication between the configurable logic units. These features lessen the impact of the data bottle-neck associated

The invention also concerns a memory device having a plurality of memory banks and configurable logic units associated with the memory banks. An interconnect is provided to enable communication between the configurable logic units. These features lessen the impact of the data bottle-neck associated with bus communications, since the processing capability is moved to the memory in the form programmable logic, which can be configured to the needs of the specific application. The inherently large on-chip bandwidth can then be utilized to increase the speed at which bulk data is processed.

대표청구항 ▼

[ We claim:] [1.] A single chip microprocessor having reprogrammable characteristics, comprising:processor for performing logic calculations in response to data input, and including a cache; andprogrammable gate array integrated with the processor and configurable by the processor, wherein the progr

[ We claim:] [1.] A single chip microprocessor having reprogrammable characteristics, comprising:processor for performing logic calculations in response to data input, and including a cache; andprogrammable gate array integrated with the processor and configurable by the processor, wherein the programmable gate array is interfaced directly with a register file of the processor and transforms logic signals being read from the cache,wherein the cache is an instruction-cache, and the programmable gate array functions as a programmable instruction decoder and cooperates with the instruction-cache to convert instructions to a new format that is compatible with the processor.