초록 ▼

Demodulation and bit synchronization apparatus that uses a plurality of field programmable gate arrays to provide parallel processing to implement demodulation and bit synchronization. An analog-to-digital converter converts and demultiplexes applied intermediate frequency signals having a substanti

Demodulation and bit synchronization apparatus that uses a plurality of field programmable gate arrays to provide parallel processing to implement demodulation and bit synchronization. An analog-to-digital converter converts and demultiplexes applied intermediate frequency signals having a substantially wide bandwidth to output demultiplexed data signals at a lower clock rate. A digital signal processor processes the demultiplexed data signals to produce detected signals. A plurality of algorithms are implemented in the demodulator and bit synchronizer that include Costas loop demodulators, for example implemented using a carrier loop/lock detector, a direct digital synthesizer and a plurality of multipliers. Eight-tap T/2 baseband equalizers are implemented using in-phase and quadrature-phase accumulators and equalizers, and an in-phase/mid-phase bit synchronizer is implemented using the in-phase accumulator and a mid-phase accumulator and equalizer. The implementation is unique in that most of the signals are demultiplexed to allow parallel processing.

대표청구항 ▼

[ What is claimed is:] [1.] A digital demodulator and bit synchronizer comprising:an analog-to-digital converter for analog to digital converting applied intermediate frequency signals having a substantially wide bandwidth to produce digital samples corresponding to the applied intermediate frequenc

[ What is claimed is:] [1.] A digital demodulator and bit synchronizer comprising:an analog-to-digital converter for analog to digital converting applied intermediate frequency signals having a substantially wide bandwidth to produce digital samples corresponding to the applied intermediate frequency signals at a first rate;a demultiplexer coupled to the analog-to-digital converter for demultiplexing the digital samples to produce a multiplicity of parallel demultiplexed data signals at a lower rate; anda digital signal processor, including a mixer, coupled to the demultiplexer for converting the multiplicity of parallel demultiplexed data signals in parallel to data signals at a frequency lower than the applied intermediate frequency, such converted data signals being output in parallel from the digital demodulator and bit synchronizer.