초록 ▼

A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a comm

A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.

대표청구항 ▼

[ What is claimed is:] [8.] Apparatus for reducing the latency of inter-reference ordering of memory reference operations in a multiprocessor system having a shared memory, the system including a first processor sharing a cache with at least a second processor, the first processor issuing a first me

[ What is claimed is:] [8.] Apparatus for reducing the latency of inter-reference ordering of memory reference operations in a multiprocessor system having a shared memory, the system including a first processor sharing a cache with at least a second processor, the first processor issuing a first memory reference operation for a data item to the system in response to a cache miss access to the shared cache for the data item, the apparatus comprising:an ordering point of the system configured to generate a commit-signal in response to the issued first memory reference operation;means for providing the data item to the shared cache in response to the issued first memory reference operation; andmeans for inheriting the commit-signal for the issued first memory reference operation at the second processor in response to a cache hit access to the shared cache for the data item to thereby maintain the reduced inter-reference ordering in the system.