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Power estimation of a microprocessor based on power consumption of memory 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-001/32
출원번호 US-0797783 (1997-02-07)
우선권정보 JP-0022811 (1996-02-08)
발명자 / 주소
  • Kageshima Atsushi,JPX
  • Usami Kimiyoshi,JPX
출원인 / 주소
  • Kabushiki Kaisha Toshiba, JPX
대리인 / 주소
    Foley & Lardner
인용정보 피인용 횟수 : 31  인용 특허 : 14

초록 ▼

A power estimator calculates the total power consumption of a microprocessor having a CPU 5, a main memory 1 and a plurality of cache memories 2, 3 and 4 based on an assembler description of a program and calculates power consumption values when an instruction to be executed by the CPU 5 is read fro

대표청구항 ▼

[ What is claimed is:] [1.] A power estimator for a microprocessor having a central processing unit (CPU) and a plurality of memories for calculating a power consumption during instruction execution in the microprocessor based on assembler descriptions of instructions to be executed, the power estim

이 특허에 인용된 특허 (14)

  1. Huck Scott B. (Beaverton OR) Lai Konrad K. (Aloha OR) Shenoy Sunil R. (Portland OR) Smith Larry O. (Beaverton OR), Apparatus and method for an instruction cache locking scheme.
    상세보기
  2. Stewart Gregory N. (Austin TX), BIOS independent power management for portable computer.
    상세보기
  3. Mathews Gregory S. (Cupertino CA) Zager Edward S. (San Jose CA), Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small writ.
    상세보기
  4. Matoba Tsukasa (Kawasaki JPX) Satou Hiroyuki (Tokyo JPX), Cache memory system having a plurality of ports.
    상세보기
  5. Crump Dwayne Thomas ; Pancoast Steven Taylor ; Steelman Herbert Stanley, Computer system having a plurality of stored system capability states from which to resume.
    상세보기
  6. Matsuo Masahito (Hyogo JPX) Yoshida Toyohiko (Hyogo JPX), Instruction fetching in data processing apparatus.
    상세보기
  7. Mozdzen Thomas J. (Gilbert AZ) Mosley Larry E. (Phoenix AZ), Method and apparatus for a microprocessor to enter and exit a reduced power consumption state.
    상세보기
  8. Witt David B. (Austin TX), Method and apparatus for testing an integrated circuit including a microprocessor and an instruction cache.
    상세보기
  9. Shermis J. Herschel (Gthenburg SEX), Method for selectively transferring data instructions to a cache memory.
    상세보기
  10. Kageshima Atsushi,JPX, Method of estimating power consumption of each instruction processed by a microprocessor.
    상세보기
  11. Debnath Kathakali (Beaverton OR) Sah Anurag (Aloha OR) Khieu Cong Quoc (San Jose CA), Power down scheme for idle processor components.
    상세보기
  12. Walsh James J. ; Kau Weiyuen, Power management supply interface circuitry, systems and methods.
    상세보기
  13. Davis Alan L. (Half Moon Bay CA) Coates William (Mountain View CA), Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruc.
    상세보기
  14. Kiuchi Atsushi (Kunitachi JPX) Nakagawa Tetsuya (Koganei JPX), System with loop buffer and repeat control circuit having stack for storing control information.
    상세보기

이 특허를 인용한 특허 (31)

  1. Fan, Xiaobo; Hennecke, Mark D.; Heath, Taliver Brooks, Accurate power allotment.
    상세보기
  2. Sandhu, Bal S.; Lattimore, George McNeil; Vineyard, Carl Wayne, Apparatus and method for obfuscating power consumption of a processor.
    상세보기
  3. Zdravkovic, Andrej, Apparatus and method for reducing power consumption of a processor by estimating engine load.
    상세보기
  4. Imada,Toyohisa; Hoshina,Takuichi, CPU power adjustment method.
    상세보기
  5. Imada,Toyohisa; Hoshina,Takuichi, CPU power adjustment method.
    상세보기
  6. Kwon, Jung Hyun; Lee, Sungeun; Jo, Sang Gu, Circuits relating to the calculation of power consumption of phase change memory devices, phase change memory systems including the same, and methods relating to the calculation of power consumption of phase change memory devices.
    상세보기
  7. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Computer and data center load determination.
    상세보기
  8. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Computer and data center load determination.
    상세보기
  9. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Computer and data center load determination.
    상세보기
  10. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Data center load monitoring for utilizing an access power amount based on a projected peak power usage and a monitored power usage.
    상세보기
  11. Ford, Simon Andrew; Bradley, Daryl Wayne; Milne, George James; Horley, John Michael, Energy management system configured to generate energy management information indicative of an energy state of processing elements.
    상세보기
  12. Greene, Michael A., Instruction scheduling based on power estimation.
    상세보기
  13. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Load control in a data center.
    상세보기
  14. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Load control in a data center.
    상세보기
  15. Hill,Stephen John, Low overhead integrated circuit power down and restart.
    상세보기
  16. Naffziger, Samuel D.; Nussbaum, Sebastien J., Managing current and power in a computing system.
    상세보기
  17. Kissell, Kevin D., Method and apparatus for disassociating power consumed within a processing system with instructions it is executing.
    상세보기
  18. Kissell, Kevin D., Method and apparatus for masking a microprocessor execution signature.
    상세보기
  19. Chris S. Browning ; Shekhar Y. Borkar ; Gregory E. Dermer, Method and apparatus for power throttling in a microprocessor using a closed loop feedback system.
    상세보기
  20. Nguyen Cau L. ; Setlur Harini G., Method and apparatus to identify a storage device within a digital system.
    상세보기
  21. Steinman, Maurice B.; Branover, Alexander J.; Krishnan, Guhan, Method for SOC performance and power optimization.
    상세보기
  22. Fan, Xiaobo; Hennecke, Mark D.; Heath, Taliver Brooks, Method of correlating power in a data center by fitting a function to a plurality of pairs of actual power draw values and estimated power draw values determined from monitored CPU utilization of a statistical sample of computers in the data center.
    상세보기
  23. Samueli, Henry; Tan, Loke K.; Putnam, Jeffrey S., Multi-mode variable rate digital cable receiver.
    상세보기
  24. Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Powering a data center.
    상세보기
  25. Alapati, Sangram; Dugar, Amit; Kumar, Prathiba; Sadasivam, Satish K., Run-time task-level dynamic energy management.
    상세보기
  26. Alapati, Sangram; Dugar, Amit; Kumar, Prathiba; Sadasivam, Satish K., Run-time task-level dynamic energy management.
    상세보기
  27. Talkin, David; Brooks, Alec, Supplying grid ancillary services using controllable loads.
    상세보기
  28. Ageishi,Narutoshi; Fukami,Yukiyasu, Synthesis mode, synthesis writing mode, and reading mode for power saving in a portable device.
    상세보기
  29. Branover, Alexander J.; Govindan, Madhu Saravana Sibi; Krishnan, Guhan; Mohapatra, Hemant R.; Lueck, Andrew W., System and method for determining a power estimate for an I/O controller based on monitored activity levels and adjusting power limit of processing units by comparing the power estimate with an assigned power limit for the I/O controller.
    상세보기
  30. Zdravkovic,Andrej, System and method for reducing power consumption by estimating engine load and reducing engine clock speed.
    상세보기
  31. Peterson, Milford J., System and method of power management for computer processor systems.
    상세보기

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