초록 ▼

An 8051 instruction set compatible microcontroller utilizing four or less clock cycles per machine cycle. The microcontroller is designed utilizing standard hardware design language techniques (HDL) and standardized cells. The microcontroller uses both a standard 8051 style special function register

An 8051 instruction set compatible microcontroller utilizing four or less clock cycles per machine cycle. The microcontroller is designed utilizing standard hardware design language techniques (HDL) and standardized cells. The microcontroller uses both a standard 8051 style special function register and a duplicate register to perform instructions requiring indirect memory accessing.

대표청구항 ▼

[ What is claimed is:] [1.] A microcontroller circuit, comprising:a RAM for storing a data address, said RAM having a plurality of storage locations;an address MUX (multiplexer) for decoding an address and for addressing a particular one of said plurality of storage locations of said RAM;a decode ci

[ What is claimed is:] [1.] A microcontroller circuit, comprising:a RAM for storing a data address, said RAM having a plurality of storage locations;an address MUX (multiplexer) for decoding an address and for addressing a particular one of said plurality of storage locations of said RAM;a decode circuit for determining whether an indirect instruction is to be performed; andan indirect addressing register for duplicatively storing said data address storable in said RAM, said indirect addressing register being connected to said decode circuit;wherein said indirect addressing register is configured to provide said data address stored in said indirect addressing register to said address MUX responsive to said decode circuit determining that an indirect instruction is to be performed by said microcontroller and wherein said data address provided by said indirect addressing register to said address MUX is directly usable by said address NUX to access said particular one of said plurality of storage locations included in said RAM.