초록 ▼

A method and system for permitting a software-based executive to execute concurrently with a hardware-based executive. The software-based executive allocates hardware executive tasks, hardware executive interrupts, software executive tasks, and software executive interrupts to defined execution spac

A method and system for permitting a software-based executive to execute concurrently with a hardware-based executive. The software-based executive allocates hardware executive tasks, hardware executive interrupts, software executive tasks, and software executive interrupts to defined execution spaces available on a microprocessor having a hardware-based executive. Applications control hardware-based executive tasks and interrupts through a hardware executive application programming interface (API), and software-based executive tasks through a software executive API. Applications share the hardware executive API functions for interrupt installation and management. The invention allocates all hardware executive interrupts to a high priority interrupt execution space, and all hardware executive tasks to a high priority queue. All software executive interrupts are allocated to low priority interrupts, and all software executive tasks are allocated to a low priority queue. The software executive uses a special context switch mechanism that changes the currently executing task without creating another low priority task. In this way, the low priority hardware scheduler is always disabled, and low priority tasks are always under the control of the software executive. A hierarchical "enables" mechanism protects critical sections of code during reentrancies. An interrupt return revectoring mechanism is provided to provide a mechanism for preemption. When a software executive interrupt occurs, the interrupt return revectoring mechanism exits the interrupt and revectors into the software kernel so that a new kernel task can begin executing, rather than returning to the previously executing task. A mechanism is also provided to accommodate block move operations.

대표청구항 ▼

[ What is claimed is:] [1.] A method for integrating a software executive within a microprocessor having an integral hardware executive, the microprocessor including a high priority scheduler, a high priority interrupt execution space, a low priority interrupt execution space, a high priority task e

[ What is claimed is:] [1.] A method for integrating a software executive within a microprocessor having an integral hardware executive, the microprocessor including a high priority scheduler, a high priority interrupt execution space, a low priority interrupt execution space, a high priority task execution queue, and a low priority task execution queue, the method including the steps of:(a) allocating all tasks controlled by the software executive to the low priority task execution queue;(b) allocating all software interrupts to the low priority interrupt execution space;(c) allocating all tasks controlled by the high priority scheduler of the hardware executive to the high priority task execution queue; and(d) allocating all hardware interrupts to the high priority interrupt execution space; reby all low priority tasks are under the control of the software executive and all high priority tasks are under the control of the hardware executive, thereby permitting hardware processes within the microprocessor to be serviced by the hardware executive as high priority tasks without interruption by tasks under the control of the software executive.