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특허 상세정보

Scheme for error control on ATM adaptation layer in ATM networks

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H03M-013/00   
미국특허분류(USC) 714/751 ; 714/701 ; 714/702 ; 714/711 ; 714/760 ; 714/752 ; 714/776 ; 370/094.1
출원번호 US-0580156 (1995-12-28)
우선권정보 JP-0326911 (1994-12-28)
발명자 / 주소
  • Nakakita Kumiko,JPX
  • Tsunoda Keiji,JPX
출원인 / 주소
  • Kabushiki Kaisha Toshiba, JPX
대리인 / 주소
    Foley & Lardner
인용정보 피인용 횟수 : 110  인용 특허 : 1
초록

A scheme for error control on AAL in ATM networks capable of realizing a reliable communication with a high throughput and a low latency. On AAL, the segmented data are sequentially written into each column of a matrix shaped data region in an interleaver, while variably setting a last column of the data region in the interleaver. Then, an error control code for the data up to the last column in each row of the data region in the interleaver is obtained and written into a corresponding location within a matrix shaped error control code region in the inte...

대표
청구항

[ What is claimed is:] [1.] A method of error control at an AAL (ATM Adaptation Layer) level, comprising the steps of:(a) segmenting continuous data to be transmitted given from an upper layer into a sequence of data in a prescribed length, and sequentially writing each data into each column of a matrix shaped data region in an interleaver;(b) variably setting a last column of the data region in the interleaver as a column of the data region in the interleaver determined in relation to one column into which a last data is written in the interleaver by th...

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