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Through the provision of first and second peripheral buses operating at different clock speeds, the integrated circuit of the present invention provides a great deal of flexibility for reducing the power consumption of the integrated circuit as compared with a similar integrated circuit having only

Through the provision of first and second peripheral buses operating at different clock speeds, the integrated circuit of the present invention provides a great deal of flexibility for reducing the power consumption of the integrated circuit as compared with a similar integrated circuit having only one peripheral bus. Since the power consumption of each peripheral bus is proportional to the clock frequency and capacitance, significant power consumption savings can be realised by ensuring that each peripheral unit is connected to the slowest peripheral bus appropriate for that peripheral unit.

대표청구항 ▼

[ We claim:] [1.] An integrated circuit comprising:a system bus to which a processor is connectable;first and second peripheral buses to which peripheral units used by said processor are connected, said first peripheral bus operating at a higher clock speed than said second peripheral bus;bridge log

[ We claim:] [1.] An integrated circuit comprising:a system bus to which a processor is connectable;first and second peripheral buses to which peripheral units used by said processor are connected, said first peripheral bus operating at a higher clock speed than said second peripheral bus;bridge logic for providing an interface between said system bus and said peripheral buses to enable signals to be passed between said system bus and said peripheral buses, said bridge logic comprising clock resynchronisation logic for synchronising said system bus and said peripheral buses.