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Vertical power MOSFET having thick metal layer to reduce distributed resistance 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
출원번호 US-0779176 (1997-01-06)
발명자 / 주소
  • Williams Richard K.
  • Kasem Mohammad
출원인 / 주소
  • Siliconix Incorporated
대리인 / 주소
    Skjerven, Morrill, MacPherson, Franklin & FrielSteuber
인용정보 피인용 횟수 : 53  인용 특허 : 22

초록

The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly

대표청구항

[ We claim:] [1.] A vertical current flow power semiconductor device comprising:a semiconductor substrate comprising a two-dimensional array of transistor cells, each of said cells comprising a first region of a first conductivity type and a body region of a second conductivity type opposite to said

이 특허에 인용된 특허 (22)

  1. Efland Taylor R. (Richardson TX) Cotton Dave (Plano TX) Skelton Dale J. (Plano TX), ESD protection structure using LDMOS diodes with thick copper interconnect.
  2. Gaw Craig A. (Scottsdale AZ) Rode Daniel L. (St. Louis MO), Electrical contact for an LED.
  3. Shimawaki, Hidenori, Heterojunction bipolar transistor having base structure for improving both cut-off frequency and maximum oscillation frequency.
  4. Larson Lawrence E. (Santa Monica CA) Asbeck Peter (San Diego CA) Brown Julia J. (Santa Monica CA), Hybrid bipolar/field-effect power transistor in group III-V material system.
  5. Baker Mark H. (San Jose CA), Method for forming solder bumps in semiconductor devices.
  6. Blanchard Richard A. (Los Altos CA), Method for making planar vertical channel DMOS structures.
  7. Kosaki Katsuya (Itami JPX), Method for manufacturing semiconductor device contact.
  8. Chikawa Yasunori (Nara JPX) Sasaki Shigeyuki (Nara JPX) Mori Katsunobu (Nara JPX) Maeda Takamichi (Nara JPX) Hayakawa Masao (Kyoto JPX), Method of manufacturing a bump electrode.
  9. Kim Manjin J. (Hartsdale NY), Method of producing VDMOS device of increased power density.
  10. Arai Hajime (Itami JPX) Furuta Isao (Itami JPX) Kuroki Hidefumi (Itami JPX) Arima Junichi (Itami JPX) Hirata Yoshihiro (Itami JPX) Harada Shigeru (Itami JPX), Method of producing semiconductor device.
  11. Temple Victor A. K. (Clifton NY) Watrous Donald L. (Clifton Park NY) Glascock ; II Homer H. (Millis MA), Package for parallel subelement semiconductor devices.
  12. Wodarczyk Paul J. (Mountaintop PA) Wheatley ; Jr. Carl F. (Drums PA) Neilson John M. S. (Norristown PA) Jones Frederich P. (Mountaintop PA), Power MOSFET transistor circuit.
  13. Kohl Paul A. (Atlanta GA) Vogt Kirkland W. (Doraville GA), Process for the low temperature creation of nitride films on semiconductors.
  14. Gray Bruce (Southbury CT) Harris James M. (Palo Alto CA) Gouin William M. (San Jose CA), Raised bonding pad.
  15. Matsumoto Hiroshi (Hyogo JPX), Semiconductor device in which wiring layer is formed below bonding pad.
  16. Korman Charles S. (Schenectady NY) Shenai Krishna (Schenectady NY), Small cell low contact resistance rugged power field effect devices and method of fabrication.
  17. Dutta Vivek B. (Cupertino CA) Demmin Jeffrey C. (Mt. View CA) DiOrio Mark L. (Cupertino CA) Ewanich Jon T. (Cupertino CA), Stadium-stepped package for an integrated circuit with air dielectric.
  18. Meyer Theodore O. (Bend OR) Mosier ; II John W. (Bend OR) Pike ; Jr. Douglas A. (Bend OR) Hollinger Theodore G. (Redmond OR) Tsang Dah W. (Bend OR), Topographic pattern delineated power MOSFET with profile tailored recessed source.
  19. Lott Joel M. (Dublin PA), Transistor device layout.
  20. Smayling Michael C. (Missouri City TX) Todd James R. (Plano TX) Hutter Louis (Richardson TX), Vertical and lateral insulated-gate, field-effect transistors, systems and methods.
  21. Williams Richard K. (Cupertino CA) Kasem Mohammad (Santa Clara CA), Vertical power mosfet having thick metal layer to reduce distributed resistance.
  22. Sato Hiroya (Tenri JPX), Vertical type construction transistor.

이 특허를 인용한 특허 (53)

  1. Parker, Scott M.; Tanghe, Steven J., Asymmetrical MOSFET layout for high currents and high speed operation.
  2. Siepe, Dirk; Gutt, Thomas; Roth, Roman, Bonding connection between a bonding wire and a power semiconductor chip.
  3. Muenzel Horst,DEX ; Offenberg Michael,DEX ; Bischof Udo,DEX ; Graf Eckhard,DEX ; Lutz Markus,DEX, Bonding pad structure and method for manufacturing the bonding pad structure.
  4. Dix, Greg; Melcher, Roger; Kline, Harold, Bumps bonds formed as metal line interconnects in a semiconductor device.
  5. Erwin A. Hijzen NL; Raymond J.E. Hueting NL, Cellular trench-gate field-effect transistors.
  6. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  7. Lin, Mou-Shiung, Chip package and method for fabricating the same.
  8. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  9. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  10. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  11. Lin,Mou Shiung, Chip structure with redistribution traces.
  12. Dikshit, Rohit; Rinehimer, Mark L.; Gruenhagen, Michael D.; Yedinak, Joseph A.; Petersen, Tracie; Sodhi, Ritu; Kinzer, Dan; Rexer, Christopher L.; Session, Fred C., Double layer metal (DLM) power MOSFET.
  13. Sutardja,Sehat; Wu,Albert; Lee,Jin Yuan; Lin,Mou Shiung, Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits.
  14. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  15. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  16. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  17. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  18. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  19. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  20. Grebs, Thomas E.; Preece, Jayson S., Multi-level options for power MOSFETS.
  21. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  22. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  23. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  24. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  25. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  26. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  27. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  28. Montgomery, Robert; Burke, Hugo; Parsonage, Philip; Johns, Susan; Jones, David Paul, Power semiconductor device including a double metal contact.
  29. Montgomery, Robert; Burke, Hugo; Parsonage, Philip; Johns, Susan; Jones, David Paul, Power semiconductor device with a double metal contact.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  31. Lin, Mou-Shiung; Yen, Huei-Mei; Lo, Hsin-Jung; Chou, Chiu-Ming; Chen, Ke-Hung, Semiconductor chip with a bonding pad having contact and test areas.
  32. Komatsu,Shigeyuki, Semiconductor device.
  33. Do, Byung Tai; Murphy, Stephen A.; Lin, Yaojian; Kuan, Heap Hoe; Marimuthu, Pandi Chelvam; Goh, Hin Hwa, Semiconductor device and method of providing common voltage bus and wire bondable redistribution.
  34. Mercado, Lei L.; Sarihan, Vijay; Chung, Young Sir; Wang, James Jen-Ho; Prack, Edward R., Semiconductor power device and method of formation.
  35. Mercado, Lei L.; Sarihan, Vijay; Chung, Young Sir; Wang, James Jen-Ho; Prack, Edward R., Semiconductor power device with shear stress compensation.
  36. Hirler,Franz, Semiconductor structure having thick stabilization layer.
  37. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  38. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  39. Dalal, Hormazdyar Minocher; Prasad, Jagdish; Ziad, Hocine Bouzid, Thick metal interconnect with metal pad caps at selective sites and process for making the same.
  40. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  51. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
  52. Chou, Chiu-Ming; Lin, Shih-Hsiung; Lin, Mou-Shiung; Lo, Hsin-Jung, Wire bonding method for preventing polymer cracking.
  53. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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