초록 ▼

A memory including an array of memory cells, each of which includes a ferroelectric field effect transistor (FET) as its memory element; and sense and refresh circuitry connected to the array of memory cells to read stored data within each cell by sensing source-to-drain conductivity of the ferroele

A memory including an array of memory cells, each of which includes a ferroelectric field effect transistor (FET) as its memory element; and sense and refresh circuitry connected to the array of memory cells to read stored data within each cell by sensing source-to-drain conductivity of the ferroelectric transistor and to refresh the stored data.

대표청구항 ▼

[ What is claimed is:] [1.] A memory comprising:an array of volatile memory cells, each of which includes as its memory element a ferroelectric field effect transistor (FET) which stores information in a polarization state that decays over time; andsense and refresh circuitry connected to the array

[ What is claimed is:] [1.] A memory comprising:an array of volatile memory cells, each of which includes as its memory element a ferroelectric field effect transistor (FET) which stores information in a polarization state that decays over time; andsense and refresh circuitry connected to the array of volatile memory cells and which during operation repeatedly reads stored data within each cell by sensing source-to-drain conductivity of the ferroelectric transistor and refreshes the stored data by restoring the ferroelectric Polarization state of the ferroelectric FETs of each cell.