초록

A digital programmable delay which provides a series of pulses that are programmed in both pulse latency and trigger latency to control the operation of a memory module test system.

대표청구항 ▼

[ What is claimed is:] [1.] A programmable pulse generator for generating a pulse signal to gate control, address, and data signals of a memory test system having a microprocessor, which comprises:a configuration register in electrical communication with said microprocessor and having stored therein

[ What is claimed is:] [1.] A programmable pulse generator for generating a pulse signal to gate control, address, and data signals of a memory test system having a microprocessor, which comprises:a configuration register in electrical communication with said microprocessor and having stored therein a trigger latency code and a pulse latency code, and a mode bit received from said microprocessor;a leading delay cell in electrical communication with said configuration register and said microprocessor, and receiving said trigger latency code and said pulse latency code from said configuration register, and a trigger signal and a latency value from said microprocessor for generating a leading edge signal for said pulse signal;trailing delay cell in electrical communication with said configuration register, said microprocessor, and said leading delay cell, and receiving said trigger latency code and said pulse latency code from said configuration register, and said trigger signal and said latency value from said microprocessor for generating a trailing edge signal for said pulse signal; anda pulse controller in electrical communication with said configuration register, said leading delay cell, and said trailing delay cell, and receiving said mode bit signal from said configuration register to select between combining said leading edge signal and said trailing edge signal to form said pulse signal, and issuing said leading edge signal and said trailing edge signal independently.