초록 ▼

In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to r

In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.

대표청구항 ▼

[ What is claimed is:] [1.] A programmable logic module for a programmable logic device comprising:programmable logic circuitry which is programmable to perform any of a plurality of logic functions on a plurality of input signals applied to said circuitry to produce a plurality of output signals in

[ What is claimed is:] [1.] A programmable logic module for a programmable logic device comprising:programmable logic circuitry which is programmable to perform any of a plurality of logic functions on a plurality of input signals applied to said circuitry to produce a plurality of output signals indicative of the logic function the circuitry has been programmed to perform, one of said logic functions being one place of binary full adder operation in which three of the input signals respectively represent two addend bits and a carry in bit and two of the output signals respectively represent a sum out bit and a carry out bit, wherein said circuitry includes register logic configured to register a signal within said circuitry and to produce a register output signal indicative of the signal thus registered, and programmable feedback logic configured to selectively allow the register output signal to be programmably selectively used as one of the input signals; andpreliminary processing componentry configured to combine two of the input signals to produce a modified input signal for said circuitry, the modified input signal being indicative of the product of the input signals combined by said componentry.