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Method and apparatus for improving the performance of digital delay locked loop circuits

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03L-007/06
출원번호 US-0081774 (1998-05-20)
발명자 / 주소
  • Miller
  • Jr. James E.
  • Schoenfeld Aaron
  • Ma Manny
  • Baker R. Jacob
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Dickerstein Sharpiro Morin & Oshinsky LLP
인용정보 피인용 횟수 : 114  인용 특허 : 10

초록

A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use o

대표청구항

[ What is claimed is new and desired to be secured by Letters Patent of the United States is:] [1.] A computer system comprising:a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; andat least one digital delay lock

이 특허에 인용된 특허 (10)

  1. Azevedo Michael J. (San Jose CA) Corchero Charles A. (Tucson AZ) Lang Donald J. (Cupertino CA) Woodman ; Jr. Gilbert R. (San Jose CA), Apparatus and method for digital compensation of oscillator drift.
  2. Chang Ray (Austin TX) Flannagan Stephen T. (Austin TX) Jones Kenneth W. (Austin TX), Delay locked loop for detecting the phase difference of two signals having different frequencies.
  3. Lee Thomas H. (Cupertino CA) Donnelly Kevin S. (San Francisco CA) Ho Tsyr-Chyang (San Jose CA) Johnson Mark G. (Los Altos CA), Delay-locked loop.
  4. Richley Edward A. (Mountian View CA), Extended frequency range variable delay locked loop for clock synchronization.
  5. Butcher James S. (Phoenix AZ), High resolution digital phase-lock loop circuit.
  6. Wang Yun-Che (Los Altos CA) Shah Gaurang (Sunnyvale CA), Means for control limits for delay locked loop.
  7. Underwood George D., Phase locked loop having memory.
  8. Sekine Shinichi (Kawasaki JPX) Asami Fumitaka (Kunitachi JPX) Kamizono Yukinori (Kawasaki JPX), Phase-difference detecting circuit and method of reducing power consumption in a PLL system.
  9. Searles Shawn (Ottawa CAX) Kusyk Richard G. (Kanata CAX), Signal delay apparatus employing a phase locked loop.
  10. Nishimichi Yoshito (Higashiosaka JPX), Timing control circuit.

이 특허를 인용한 특허 (114)

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