초록 ▼

A control apparatus for controlling a three phase load apparatus. The control apparatus includes a voltage source inverter having a first pair of transistors, a second pair of transistors, and a third pair of transistors. Each such pair of transistors is connected serially between the terminals of a

A control apparatus for controlling a three phase load apparatus. The control apparatus includes a voltage source inverter having a first pair of transistors, a second pair of transistors, and a third pair of transistors. Each such pair of transistors is connected serially between the terminals of a voltage source. The activation of a first transistor in each such pair of such transistors is effected by the application thereto of a first activation voltage, a second activation voltage and a third activation voltage, respectively, causing a first phase voltage, a second phase voltage and a third phase voltage, to be applied to a respective one of the three parts of the three-phase load apparatus. The selection and duration of activation of such first transistors during each of a continuing series of equal time periods T.sub.p is symmetrical about the mid-point of each of the time periods, and is represented by six non-zero vectors and two zero vectors. The control apparatus also includes a processor, and a bus coupled to the processor for communicating data between the processor and other control apparatus elements. The control apparatus also includes a counter coupled to the bus for providing a counter value counting from zero up to a value of one half of T.sub.p and then counting down to zero, for each of the equal time periods T.sub.p. A compare unit is also included, coupled to the bus, having a plurality of registers for the storage of transition count values corresponding to the transition times between the activations of the first transistors in accordance with predetermined space vectors, for comparing the counter value against the transition count values and providing respective transition timing signals when the counter value is the same as the transition count values. Finally, a state machine is included, coupled to the bus and to the compare unit for generating the first activation voltage, the second activation voltage and the third activation voltage and providing them to the voltage source inverter in response to the respective transition timing signals.

대표청구항 ▼

[ What is claimed is:] [1.] A control apparatus for controlling a three phase load apparatus, comprising:a voltage source inverter comprisinga first pair of transistors,a second pair of transistors,a third pair of transistors,each such pair of transistors being connected serially between the termina

[ What is claimed is:] [1.] A control apparatus for controlling a three phase load apparatus, comprising:a voltage source inverter comprisinga first pair of transistors,a second pair of transistors,a third pair of transistors,each such pair of transistors being connected serially between the terminals of a voltage source, the activation of a first transistor in each such pair of such transistors by the application thereto of a first activation voltage, a second activation voltage and a third activation voltage, respectively, causing a first phase voltage, a second phase voltage and a third phase voltage, to be applied to a respective one of the three parts of said three-phase load apparatus, the selection and duration of activation of said first transistors during each of a continuing series of equal time periods T.sub.p represented by six non-zero vectors and two zero vectors;a processor;a bus coupled to said processor for communicating data between said processor and other control apparatus elements;a counter coupled to said bus for providing a counter value counting from a first value to a second value during one half of T.sub.p and then counting from said second value to said first value during a second half of T.sub.p, for each of said equal time periods T.sub.p ;a compare unit coupled to said bus, having a plurality of registers for the storage of transition count values corresponding to the transition times between said activations of said first transistors in accordance with predetermined space vectors, for comparing said counter value against said transition count values and providing respective transition timing signals when said counter value is the same as said transition count values;a state machine coupled to said bus and to said compare unit for generating said first activation voltage, said second activation voltage and said third activation voltage and providing them to said voltage source inverter in response to said respective transition timing signals.