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Air gap formation for high speed IC processing 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0236493 (1999-01-25)
발명자 / 주소
  • Liu Erzhuang,SGX
출원인 / 주소
  • Chartered Semiconductor Manufacturing, Ltd., SGX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 59  인용 특허 : 31

초록 ▼

The process of the present invention can be used for conventional processing or for the Damascene process. The key concept of the present invention is a functional "filler" material which can later be removed (decomposed) to leave an air gap between the conducting lines. The filler material can be d

대표청구항 ▼

[ What is claimed is:] [1.] A method of forming air gaps between metal leads of a semiconductor device, comprising the steps of:securing a semiconductor wafer;forming a base layer on said semiconductor wafer;depositing a metal layer on said base layer;etching said metal layer in a pattern to form me

이 특허에 인용된 특허 (31)

  1. Hause Fred N. ; Bandyopadhyay Basab ; Dawson Robert ; Fulford ; Jr. H. Jim ; Michael Mark W. ; Brennan William S., Dissolvable dielectric method.
    상세보기
  2. Jeng Shin-puu ; Havemann Robert H., Interconnect capacitance between metal leads.
    상세보기
  3. Aitken John M. (Mahopac NY) Beyer Klaus D. (Poughkeepsie NY) Crowder Billy L. (Putnam Valley NY) Greco Stephen E. (Lagrangeville NY), Larce scale IC personalization method employing air dielectric structure for extended conductors.
    상세보기
  4. Gnade Bruce E. ; Cho Chih-Chen ; Smith Douglas M., Low dielectric constant layers via immiscible sol-gel processing.
    상세보기
  5. Nagabushnam Rajan ; Bajaj Rajeev ; Venkataraman Ram ; Mattay Shyam ; Iyer Subramoney V., Method for using a conductive tungsten nitride etch stop layer to form conductive interconnects and tungsten nitride contact structure.
    상세보기
  6. Chang Mark S. (Los Altos CA) Cheung Robin W. (Cupertino CA), Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed perfo.
    상세보기
  7. Klatskin Jerome Barnard (Princeton Junction NJ) Rosen Arye (Cherry Hill NJ), Method of electrically interconnecting semiconductor elements.
    상세보기
  8. Shaheen Joseph M. (La Habra CA) Simone John (Stanton CA), Method of fabricating a beam lead flexible circuit.
    상세보기
  9. Hirano Makoto (Tokyo JPX) Asai Kazuyoshi (Atsugi JPX) Imai Yuhki (Sagamihara JPX) Tokumitsu Masami (Isehara JPX) Tokumitsu Tsuneo (Yokosuka JPX) Toyoda Ichihiko (Yokosuka JPX), Method of fabricating circuit elements on an insulating substrate.
    상세보기
  10. Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Method of forming a semiconductor structure having an air region.
    상세보기
  11. Conti Richard A. (Mount Kisco NY) DeVries Kenneth (Hopewell Junction NY) White James F. (Newburgh NY), Method of forming metal connections.
    상세보기
  12. Numata Ken (Dallas TX), Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layer.
    상세보기
  13. Numata Ken,JPX ; Houston Kay, Method of making reliable metal leads in high speed LSI semiconductors using dummy leads.
    상세보기
  14. Numata Ken (Dallas TX), Method of making reliable metal leads in high speed LSI semiconductors using thermoconductive layers.
    상세보기
  15. Bai Gang, Method to fabricate unlanded vias with a low dielectric constant material as an intraline dielectric.
    상세보기
  16. Dawson Robert ; Michael Mark W. ; Brennan William S. ; Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Hause Fred N., Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect.
    상세보기
  17. Havemann Robert H. (Garland TX) Jeng Shin-puu (Plano TX), Multilevel interconnect structure with air gaps formed between metal leads.
    상세보기
  18. Havemann Robert H. (Plano TX) Jeng Shin-puu (Plano TX), Multilevel interconnect structure with air gaps formed between metal leads.
    상세보기
  19. Jeng Shin-Puu (2508 Evergreen Dr. Plano TX 75075), Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators.
    상세보기
  20. Jeng Shin-Puu (Plano TX), Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators.
    상세보기
  21. Jeng Shin-Puu (Plano TX), Planarizeed multi-level interconnect scheme with embedded low-dielectric constant insulators.
    상세보기
  22. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
    상세보기
  23. Hirano Makoto (Tokyo JPX) Asai Kazuyoshi (Atsugi JPX) Imai Yuhki (Sagamihara JPX) Tokumitsu Masami (Isehara JPX) Tokumitsu Tsuneo (Yokosuka JPX) Toyoda Ichihiko (Yokosuka JPX), Process of fabricating a circuit element for transmitting microwave signals.
    상세보기
  24. Numata Ken (14332 Montfort ; Apt. #6306 Dallas TX 75240), Reliability of metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers.
    상세보기
  25. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
    상세보기
  26. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
    상세보기
  27. Numata Ken, Reliable metal leads in high speed LSI semiconductors using dummy leads.
    상세보기
  28. Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Semiconductor structure having an air region and method of forming the semiconductor structure.
    상세보기
  29. Grill Alfred ; Saenger Katherine Lynn, Structure and fabrication method for stackable, air-gap-containing low epsilon dielectric layers.
    상세보기
  30. Havemann Robert H., Structure with selective gap fill of submicron interconnects.
    상세보기
  31. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
    상세보기

이 특허를 인용한 특허 (59)

  1. Lur,Water; Lee,David; Wang,Kuang Chih; Yang,Ming Sheng, Air gap for dual damascene applications.
    상세보기
  2. Lur,Water; Lee,David; Wang,Kuang Chih; Yang,Ming Sheng, Air gap for tungsten/aluminum plug applications.
    상세보기
  3. Gallagher,Michael K.; Gronbeck,Dana A.; Adams,Timothy G.; Calvert,Jeffrey M., Air gap formation.
    상세보기
  4. Lur,Water; Lee,David; Wang,Kuang Chih; Yang,Ming Sheng, Air gap formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device.
    상세보기
  5. Demos, Alexandros T.; Xia, Li-Qun; Kim, Bok Hoen; Witty, Derek R.; M'Saad, Hichem, Air gap integration scheme.
    상세보기
  6. Park, Hyun-Mog; Kloster, Grant M., Air gap interconnect method.
    상세보기
  7. Park,Hyun Mog; Kloster,Grant M., Air gap interconnect structure and method.
    상세보기
  8. Lur, Water; Lee, David; Wang, Kuang-Chih; Yang, Ming-Sheng, Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device.
    상세보기
  9. Kloster, Grant; Leu, Jihperng; Park, Hyun-Mog, Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material.
    상세보기
  10. Farrar, Paul A., Damascene structure and method of making.
    상세보기
  11. Paul A. Farrar, Damascene structure and method of making.
    상세보기
  12. Farrar, Paul A., Damascene structure with low dielectric constant insulating layers.
    상세보기
  13. Zhou Mei Sheng,SGX ; Chooi Simon,SGX ; Yi Xu,SGX, Dual metal-oxide layer as air bridge.
    상세보기
  14. Gallagher, Michael K.; Gronbeck, Dana A.; Adams, Timothy G.; Calvert, Jeffrey M., Electronic devices having air gaps.
    상세보기
  15. Kohl Paul A. ; Zhao Qiang ; Bidstrup Allen Sue Ann, Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections.
    상세보기
  16. Kohl,Paul A.; Zhao,Qiang; Bidstrup Allen,Sue Ann, Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections.
    상세보기
  17. Kohl, Paul Albert; Allen, Sue Ann Bidstrup; Henderson, Clifford Lee; Reed, Hollie Anne; Bhusari, Dhananjay M., Fabrication of semiconductor device with air gaps for ultra low capacitance interconnections and methods of making same.
    상세보기
  18. Kohl, Paul Albert; Allen, Sue Ann Bidstrup; Henderson, Clifford Lee; Reed, Hollie Ann; Bhusari, Dhananjay M., Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnections and methods of making same.
    상세보기
  19. Anand Minakshisundaran Balasubramanian,JPX ; Shibata Hideki,JPX ; Yamada Masaki,JPX, Feasible, gas-dielectric interconnect process.
    상세보기
  20. Torres, Joaquim; Arnal, Vincent; Farcy, Alexis, High-frequency line.
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  21. Pamler,Werner; Schwarzl,Siegfried; Gabric,Zvonimir, Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit.
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  22. Bergendahl, Marc A.; Demarest, James J.; Penny, Christopher J.; Waskiewicz, Christopher J., Hybrid airgap structure with oxide liner.
    상세보기
  23. Camillo-Castillo, Renata A.; Dunn, James S.; Harame, David L.; Stamper, Anthony K., Integrated circuit structure having air-gap trench isolation and related design structure.
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  24. Camillo-Castillo, Renata A.; Dunn, James S.; Harame, David L.; Stamper, Anthony K., Integrated circuit structure having air-gap trench isolation and related design structure.
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  25. Chi, Chih-Chien; Su, Hung-Wen, Interconnect structure having air gap and method of forming the same.
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  26. Chi, Chih-Chien; Su, Hung-Wen, Interconnect structure having air gap and method of forming the same.
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  27. Demolliens, Olivier; Berruyer, Pascale; Trouiller, Yorick; Morand, Yves, Method for fabricating a structure of interconnections comprising an electric insulation including air or vacuum gaps.
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  28. Seng Keong Victor Lim SG; Young-way Teh SG; Ting-Cheong Ang SG; Alex See SG; Yong Kong Siew SG, Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures.
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  29. Victor Seng Keong Lim SG; Young-Way Teh SG; Ting-Cheong Ang SG; Alex See SG; Yong Kong Siew MY, Method for fabricating an air gap shallow trench isolation (STI) structure.
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  30. Coronel, Philippe; Laplanche, Yves; Pain, Laurent, Method for forming under a thin layer of a first material portions of another material and/or empty areas.
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  31. Coronel,Philippe; Laplanche,Yves; Pain,Laurent, Method for forming, under a thin layer of a first material, portions of another material and/or empty areas.
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  32. Lin Shih-Chi,TWX ; Chen Yen-Ming,TWX, Method for manufacturing arch air gap in multilevel interconnection.
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  33. Horak, David Vaclav; Koburger, III, Charles William; Mitchell, Peter H.; Nesbit, Larry Alan, Method for supporting a bond pad in a multilevel interconnect structure and support structure formed thereby.
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  34. Fitz, John L.; Turk, Harris, Method of fabricating a patterned device using sacrificial spacer layer.
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  35. Fitz, John L.; Turk, Harris, Method of fabricating a patterned device using sacrificial spacer layer.
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  36. Fitz, John L.; Turk, Harris, Method of fabricating a patterned device using sacrificial spacer layer.
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  37. Fitz,John Leslie; Turk,Harris, Method of fabricating a patterned device using sacrificial spacer layer.
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  38. Joaquim Torres FR; Philippe Gayet FR; Michel Haond FR, Method of forming insulated metal interconnections in integrated circuits.
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  49. Kirchhoff, Robert A.; Niu, Jason Q.; Li, Yongfu; Foster, Kenneth L., Sacrificial benzocyclobutene copolymers for making air gap semiconductor devices.
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  52. Furuhashi, Takashi; Shimada, Miyoko; Mizushima, Ichiro; Nakao, Shinichi, Semiconductor device with air gap therein and manufacturing method thereof.
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  55. Lee, Henry F., Semiconductor fabrication process and structure with minimal capacitive coupling between conductors.
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  57. Lo, Guo-Qiang (Patrick); Schorr, Brian; Foley, Gary; Lee, Shih-Ked, Stress-relieved shallow trench isolation (STI) structure and method for forming the same.
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  58. Lo,Guo Qiang (Patrick); Schorr,Brian; Foley,Gary; Lee,Shih Ked, Stress-relieved shallow trench isolation (STI) structure and method for forming the same.
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