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Method for preventing poisoned vias and trenches 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0152921 (1998-09-14)
우선권정보 TW-0112282 (1998-07-28)
발명자 / 주소
  • Wu Kun-Lin,TWX
  • Lu Horng-Bor,TWX
출원인 / 주소
  • United Microelectronics Corp., TWX
대리인 / 주소
    Thomas, Kayden, Horstemeyer & Risley
인용정보 피인용 횟수 : 27  인용 특허 : 15

초록

A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an electron-beam process, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive mater

대표청구항

[ What is claimed is:] [1.] A method for preventing poisoned trenches and vias, the method comprising;providing a substrate, wherein the substrate further comprises a conducting layer;forming a dielectric layer on the substrate;forming a trench and a via hole in the dielectric layer, wherein the tre

이 특허에 인용된 특허 (15)

  1. Yu Chen-Hua Douglas,TWX ; Jang Syun Ming,TWX, Dual damascene patterned conductor layer formation method without etch stop layer.
  2. Yew Tri-Rung,TWX ; Lur Water,TWX ; Sun Shih-Wei,TWX ; Huang Yimin,TWX, Fabricating method of a barrier layer.
  3. Jang Syun-Ming,TWX ; Huang Ming-Hsin,TWX, Hard masking method for forming oxygen containing plasma etchable layer.
  4. Janke Christopher J. ; Lopata Vincent J.,CAX ; Havens Stephen J. ; Dorsey George F. ; Moulton Richard J., High energy electron beam curing of epoxy resin systems incorporating cationic photoinitiators.
  5. Cooper Kent J. (Austin TX) Lin Jung-Hui (Austin TX) Roth Scott S. (Austin TX) Roman Bernard J. (Austin TX) Mazure Carlos A. (Austin TX) Nguyen Bich-Yen (Austin TX) Ray Wayne J. (Austin TX), Method for forming contact to a semiconductor device.
  6. Fiordalice Robert W. (Austin TX) Maniar Papu D. (Austin TX) Klein Jeffrey L. (Austin TX), Method for forming inlaid interconnects in a semiconductor device.
  7. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  8. Chiang Chien ; Fraser David B., Method for forming multileves interconnections for semiconductor fabrication.
  9. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  10. Mo Roy (Flushing NY), Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition.
  11. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  12. Godschalx James P. ; Romer Duane R. ; So Ying Hung ; Lysenko Zenon ; Mills Michael E. ; Buske Gary R. ; Townsend ; III Paul H. ; Smith ; Jr. Dennis W. ; Martin Steven J. ; DeVries Robert A., Polyphenylene oligomers and polymers.
  13. Heitzmann Michel (Crolles FRX) Lajzerowicz Jean (Meylan FRX) LaPorte Philippe (Sassenage FRX), Process for etching and depositing integrated circuit interconnections and contacts.
  14. Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.
  15. Avanzino Steven (Cupertino CA) Gupta Subhash (San Jose CA) Klein Rich (Mountain View CA) Luning Scott D. (Menlo Park CA) Lin Ming-Ren (Cupertino CA), Subtractive dual damascene.

이 특허를 인용한 특허 (27)

  1. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  2. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  3. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Chip structure and process for forming the same.
  4. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.
  5. Liu Haochieh,TWX, Fabrication method for dual damascene structure.
  6. Restaino, Darryl D.; Hedrick, Jeffrey C.; Fitzsimmons, John A.; Tyberg, Christy S.; Liu, Chih-Chien; Siddiqui, Shahab, Film planarization for low-k polymers used in semiconductor structures.
  7. Naoki Komai JP; Shingo Kadomura JP; Mitsuru Taguchi JP; Akira Yoshio JP; Takaaki Miyamoto JP, Interconnection structure and fabrication process therefor.
  8. Cook Robert ; Greco Stephen E. ; Hummel John P. ; Liu Joyce ; McGahay Vincent J. ; Mih Rebecca ; Srivastava Kamalesh, Interim oxidation of silsesquioxane dielectric for dual damascene process.
  9. Layadi Nace ; Merchant Sailesh Mansinh ; Molloy Simon John ; Roy Pradip Kumar, Method for forming vias in a low dielectric constant material.
  10. Restaino, Darryl D.; Bennett, Delores; Fitzsimmons, John A.; Fritche, John; Hedrick, Jeffrey C.; Liu, Chih-Chien; Siddiqui, Shahab; Tyberg, Christy S., Method for reworking low-k polymers used in semiconductor structures.
  11. Nallan, Padmapani, Method of etching a tantalum nitride layer in a high density plasma.
  12. Matsumoto Akira,JPX, Method of fabricating a semiconductor structure.
  13. Lou Chine-Gie,TWX, Method of fabricating dual damascene structure.
  14. Taniguchi, Kensuke, Method of fabricating semiconductor device.
  15. Taniguchi, Kensuke, Method of fabricating semiconductor device.
  16. Liu Jen-Cheng,TWX ; Tsai Chia-Shia,TWX, Method to fabricate self-aligned dual damascene structures.
  17. Chittipeddi, Sailesh, Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor.
  18. Kudo,Hiroshi; Ikeda,Masanobu; Watanabe,Kenichi; Ohkura,Yoshiyuki, Semiconductor device having a multilayer interconnection structure.
  19. Subramanian, Ramkumar; Lukanc, Todd P.; Wang, Fei, Slotted trench dual inlaid structure and method of forming thereof.
  20. Lin, Jing-Cheng; Shue, Shau-Lin, Thermal annealing/hydrogen containing plasma method for forming structurally stable low contact resistance damascene conductor structure.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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