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특허 상세정보

Priority arbiter with shifting sequential priority scheme

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-017/30   
미국특허분류(USC) 707/09 ; 707/01 ; 707/010 ; 710/100 ; 710/111 ; 710/116 ; 710/117 ; 710/241 ; 710/200
출원번호 US-0049500 (1998-03-27)
발명자 / 주소
출원인 / 주소
인용정보 피인용 횟수 : 96  인용 특허 : 13
초록

An improved data processing system and in particular an improved data processing system that more effectively manages a shared resource within a data processing system. More specifically, a method and apparatus for managing access to a shared resource between a plurality of devices simultaneously requesting access to the shared resource. The present invention implements a design that combines a priority configuration and a shifting sequential configuration. The access is controlled by an arbiter that determines access to the shared resource by granting f...

대표
청구항

[ What is claimed is:] [24.] A data processing system, comprising:a plurality of devices, the plurality of devices including a plurality of shifting priority devices; andan arbiter, wherein the arbiter receives requests from the plurality of devices for access to a shared resource, and wherein if one of the plurality of devices is a priority device, the arbiter chooses the priority device to access the shared resource, and if a priority device is absent, the arbiter chooses a device having a highest priority from of the plurality of shifting priority dev...

이 특허에 인용된 특허 (13)

  1. Chen Ray (Folsom CA) Rabe Jeffrey L. (Gold River CA). Arbiter and arbitration process for a dynamic and flexible prioritization. USP1996085546548.
  2. Buch Bruce D. (Westborough MA) MacGregor Cecil D. (Milford MA). Arbiter with programmable dynamic request prioritization. USP1994045303382.
  3. Bomba Frank C. (Andover MA) Strecker William D. (Harvard MA) Jenkins Steven R. (Acton MA). Arbitration mechanism for assigning control of a communications path in a digital computer system. USP1988114787033.
  4. Sato Masami (Ishikawa JPX) Goto Yuichi (Kawasaki JPX). Bus arbiter and bus arbitrating method. USP1996125583999.
  5. Bass Brian M. (Wake NC) Ku Edward H. (Wake NC) Lin Bou-Chung (Wake NC) Sanaye Simin H. (Wake NC). Data processing system having dynamic priority task scheduling capabilities. USP1996015487170.
  6. McKinney Steven J. (Coral Springs FL) Earnshaw William E. (N. Lauderdale FL). Dual rotating priority arbitration method for a multiprocessor memory bus. USP1990054924380.
  7. Levenstein Sheldon B. (Rochester MN). Duplicated logic and interconnection system for arbitration among multiple information processors. USP1996125586331.
  8. Levenstein Sheldon B. (Rochester MN). Duplicated logic and interconnection system for arbitration among multiple information processors. USP1996105566305.
  9. Gallagher Andrew M. (Long Beach NY). Multimode resource arbiter providing round robin arbitration or a modified priority arbitration. USP1991125072363.
  10. Whittaker Bruce E. (Mission Viejo CA) Barajas Saul (Capistrano Beach CA) Watson Leland E. (Mission Viejo CA). Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests. USP1992095146596.
  11. Oman Price W. (Raleigh NC) Rindos ; III Andrew J. (Durham NC). Priority generator for providing controllable guaranteed fairness in accessing a shared bus. USP1995025392033.
  12. Narayanan C. Murali (Wheaton IL) Zee Benjamin (Oak Park IL). Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements. USP1989034814974.
  13. O\Connell Anne (Galway IEX) Creedon Tadhg (Galway IEX) Smith Deidre A. (Kildare IEX). Programmable priority arbiter. USP1993085241632.

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