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Integrated circuit bonding method and apparatus 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/48
  • H01L-021/50
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0238706 (1999-01-28)
발명자 / 주소
  • Degani Yinon
  • Greenberg Lawrence Arnold
출원인 / 주소
  • Lucent Technologies Inc.
인용정보 피인용 횟수 : 44  인용 특허 : 9

초록

A technique for enabling sufficient flow of flux cleaning fluids and an underfill material in the relatively low-profile gap between a flip-chip bonded IC chip and a substrate, such as a printed circuit board, is to provide at least one aperture in the substrate under the IC chip. The use of such an

대표청구항

[ What is claimed is:] [7.] A method for bonding an integrated circuit chip to a substrate comprising:providing at least one aperture in a major surface of said substrate;bonding at least two contact pads of said integrated circuit to matching contact pads on said major substrate surface to from cor

이 특허에 인용된 특허 (9)

  1. Murphy Walter T. (Cuyahoga Falls OH) Guiley ; Jr. Clifford D. (Medina OH), Curable thixotropic epoxy/amine terminated liquid polymer compositions.
  2. Chau Michael M. ; Burkhart Donald A., Materials for semiconductor device assemblies.
  3. Breunsbach Rex (14732 SE. 117th Ave. Clackamas OR 97015), Method for cleaning electronic assemblies.
  4. Sweis Jason (Sunnyvale CA) Gilleo Kenneth B. (West Kingston RI), Method of forming interface between die and chip carrier.
  5. Distefano Thomas H. ; Smith ; Jr. John W., Microelectronics unit mounting with multiple lead bonding.
  6. Beddingfield Stanley C. ; Higgins ; III Leo M. ; Gentile John C., Process for underfilling a flip-chip semiconductor device.
  7. Papathomas Kostas I. (Endicott NY) Wang David Wei (Vestal NY), Solder interconnection structure.
  8. Degani Yinon (Highland Park NJ), Solder paste and method of using the same.
  9. Degani Yinon (Highland Park NJ), Soldering material and procedure.

이 특허를 인용한 특허 (44)

  1. Susheel,Jadhav G.; Lu,Daoqiang, Apparatus and method for attaching a semiconductor die to a heat spreader.
  2. Brandenburger, Peter D., Apparatus and methods for an underfilled integrated circuit package.
  3. Weber Patrick O., Chip package with molded underfill.
  4. Weber, Patrick O., Chip package with molded underfill.
  5. Lee,Teck Kheng; Lee,Kian Chai; Khoo,Sian Yong, Double bumping of flexible substrate for first and second level interconnects.
  6. Ogawa, Toshio; Takahashi, Masaaki; Kamimura, Noritaka; Yamada, Kazuji; Kaminaga, Toshiaki, Electronic device and method of fabricating the same.
  7. Lee, Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
  8. Lee, Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
  9. Lee,Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
  10. Lee,Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
  11. Moon,Ow Chee; Koon,Eng Meow, Flexible ball grid array chip scale packages.
  12. Lee, Teck Kheng, Flip chip packaging using recessed interposer terminals.
  13. Lee,Teck Kheng, Flip chip packaging using recessed interposer terminals.
  14. Ofner, Gerald; Yeo, Swain Hong; Teo, Mary; Lim, Pei Siang; Chua, Khoon Lam, Integrated circuit package and a method for forming an integrated circuit package.
  15. Lee,Teck Kheng, Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods.
  16. Lee,Teck Kheng, Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured semiconductor dice.
  17. Abhay Maheshwari ; Shirish Shah, Method and apparatus for cleaning and removing flux from an electronic component package.
  18. Lee, Teck Kheng, Method and apparatus for dielectric filling of flip chip on interposer assembly.
  19. Jadhav,Susheel G.; Lu,Daoqiang, Method for attaching a semiconductor die to a substrate and heat spreader.
  20. Fujisawa, Atsushi; Konno, Takafumi; Ohsaka, Shingo; Haruta, Ryo; Ichitani, Masahiro, Method of manufacturing a resin encapsulated semiconductor device to provide a vent hole in a base substrate.
  21. Lee, Teck Kheng, Method of manufacturing microelectronic devices, including methods of underfilling microelectronic components through an underfill aperture.
  22. Patrick O. Weber, Method of underfilling an integrated circuit chip.
  23. Lee, Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
  24. Lee,Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
  25. Lee,Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
  26. Lee, Teck Kheng; Tan, Cher Khng Victor, Methods of forming semiconductor assemblies.
  27. Kim, KyungHwan; Yang, DeokKyung; Mun, SeongHun; Lee, KeoChang, Methods of mitigating defects for semiconductor packages.
  28. Takahashi Kazuaki,JPX ; Sangawa Ushio,JPX, Millimeter wave module and radio apparatus.
  29. Takahashi Kazuaki,JPX ; Sangawa Ushio,JPX, Millimeter wave module and radio apparatus.
  30. Takahashi, Kazuaki; Sangawa, Ushio, Millimeter wave module and radio apparatus.
  31. Takahashi, Kazuaki; Sangawa, Ushio, Millimeter wave module and radio apparatus.
  32. Hou, Hao-Cheng; Chen, Yu-Feng; Cheng, Jung Wei; Liang, Yu-Min; Wang, Tsung-Ding, Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices.
  33. Hou, Hao-Cheng; Chen, Yu-Feng; Cheng, Jung Wei; Liang, Yu-Min; Wang, Tsung-Ding, Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices.
  34. Jang, Jaegwon; Kim, Youngjae; Lee, Baikwoo, Printed circuit board.
  35. Teysseyre,J챕r척me, Process for encapsulating semiconductor components using through-holes in the semiconductor components support substrates.
  36. Lee, KyungHoon; Yang, JoungIn; Park, Sang Mi; Choi, DaeSik; Park, YiSu, Semiconductor device and method of depositing underfill material with uniform flow rate.
  37. Lee, Teck Kheng, Semiconductor device assemblies.
  38. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures.
  39. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures and methods for assembling the same.
  40. Yu, Tsung-Yuan, Semiconductor package device and forming the same.
  41. Fritz, Donald S., Semiconductor package with stress inhibiting intermediate mounting substrate.
  42. Fritz, Donald S., Semiconductor package with stress inhibiting intermediate mounting substrate.
  43. Lewis, J. Shelton; Lloyd, Shawn; Kochanowski, Michael; Oldendorf, John, Via heat sink material.
  44. Lewis,J. Shelton; Lloyd,Shawn; Kochanowski,Michael; Oldendorf,John, Via heat sink material.
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