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특허 상세정보

Technique for reducing peak current in memory operation

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G11C-007/00   
미국특허분류(USC) 365/203 ; 365/205
출원번호 US-0198062 (1998-11-23)
발명자 / 주소
출원인 / 주소
인용정보 피인용 횟수 : 7  인용 특허 : 19
초록

A circuit in a memory device and a method for precharging at least one bit line in the memory device. The circuit includes a primary precharger and a secondary precharger in communication with the bit line. The secondary precharger gradually precharges the bit line before the primary precharger precharges the bit line between memory operations.

대표
청구항

[ What is claimed is:] [9.] A circuit in a dynamic random access memory for precharging at least one bit line in the memory device, said circuit comprising:a primary precharger in communication with the bit line;a secondary precharger in communication with the bit line, wherein said secondary precharger gradually precharges the bit line before said primary precharger precharges the bit line between memory operations, wherein said secondary precharger includes at least one pullup device which is smaller than a pullup device of said primary precharger, and...

이 특허에 인용된 특허 (19)

  1. Han Yong-joo,KRX. Circuit and method for controlling bit line for a semiconductor memory device. USP1999115982688.
  2. An Jin H. (Kyungki-do KRX). DRAM having bidirectional global bit lines. USP1994115367488.
  3. Tsuchida Kenji,JPX. Dynamic semiconductor memory device having a precharge circuit using low power consumption. USP1998095815451.
  4. Lee Jin-Young,KRX. Internal voltage boosting method and circuit for a semiconductor memory device. USP1998015706230.
  5. Tai Jy-Der David,TWX. Low power dynamic random access memory. USP1998015710738.
  6. Pham Luat Q. ; Cano Francisco A.. Method and apparatus for self-timed precharge of bit lines in a memory. USP1998045745421.
  7. Kwon Kook-hwan,KRX ; Park Hee-choul,KRX. Precharge system for a semiconductor memory device. USP1999105973972.
  8. Proebsting Robert J.. Self adjusting delay circuit and method for compensating sense amplifier clock timing. USP1999085936905.
  9. Yamauchi Tatsumi,JPX ; Murabayashi Fumio,JPX. Semiconductor integrated circuit device. USP1999055903503.
  10. Hisada Toshiki (Yokohama JPX) Koinuma Hiroyuki (Yokohama JPX). Semiconductor integrated circuit having a voltage booster and precharging circuit. USP1997045623446.
  11. Suda Kei (Tokyo JPX) Furuya Nobuo (Tokyo JPX). Semiconductor memory device. USP1995055418749.
  12. Nishimura Koichi (Kawasaki JPX) Matsumiya Masato (Kawasaki JPX). Semiconductor memory device having dual boosting circuits to reduce energy required to supply boosting voltages. USP1997125703814.
  13. Inoue Kouji,JPX. Semiconductor memory device with dual precharge operations. USP1998065768199.
  14. Choi Jong-Hyun,KRX ; Hwang Hong-Sun,KRX. Semiconductor memory device with on-chip boosted power supply voltage generator. USP1998055757714.
  15. Lee Sang-bo,KRX ; Seo Dong-il,KRX. Semiconductor memory device with variable plate voltage generator. USP1998075777934.
  16. Sato Hiroshi,JPX ; Yamazaki Takashi,JPX. Semiconductor nonvolatile memory device in which high capacitance bit lines are isolated from sense amplifier input/out. USP1999115978271.
  17. Jang Cheol-Ung,KRX. Semiconductor read only memory and a method for reading data stored in the same. USP1999035886937.
  18. Kongetira Poonacha. Single ended match sense amplifier. USP1999085936873.
  19. Jeon Jun-young,KRX. Voltage boosting circuit having dual precharge circuits in semiconductor memory device. USP1998125850363.