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Hardware-based system for enabling data transfers between a CPU and chip set logic of a computer system on both edges of bus clock signal

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/00
출원번호 US-0974970 (1997-11-20)
발명자 / 주소
  • Wisor Michael T.
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Conley, Rose & Tayon, PCKivlin
인용정보 피인용 횟수 : 22  인용 특허 : 12

초록

A hardware-based system for configuring a CPU and chip set logic of a computer system to allow data transfers on both the rising and falling edges of a bus clock signal. The CPU and chip set logic each include bus communication circuitry for transferring data, a storage unit, and a configuration cir

대표청구항

[ What is claimed is:] [10.] A central processing unit (CPU), comprising:a bus communication circuit having:a first data transfer mode effectuating data transfers on a single transition of a bus clock signal; anda second data transfer mode effectuating data transfers on both transitions of the bus c

이 특허에 인용된 특허 (12)

  1. Okamoto Masato,JPX, Electronic control apparatus for vehicle.
  2. McClure David C. (Carrollton TX), Full memory chip long write test mode.
  3. Gates Stillman F., Integrated circuit with a serial port having only one pin.
  4. Schauss Craig A. (Decatur IN) Neumann Donald E. (Huntington Woods MI) Bielawski Dennis A. (Romeo MI), Interface chip device.
  5. Conary James W. (Aloha OR) Beutler Robert R. (Lake Oswego OR), Method and apparatus for invalidating a cache while in a low power state.
  6. Mote ; Jr. L. Randall, Method and apparatus for reducing cumulative time delay in synchronizing transfer of buffered data between two mutually.
  7. Lo, Yuan-Chang, Multiple access data communication system.
  8. Sasaki Takayoshi (Tokyo JPX) Miura Katsumi (Tokyo JPX), Register circuit for copying contents of one register into another register.
  9. Matsushima Osamu (Tokyo JPX) Maehashi Yukio (Tokyo JPX), Serial data processor capable of transferring data at a high speed.
  10. Walsh James J. ; Joe Joseph ; Milhaupt Robert W. ; Bridgwater James,GB6 ; Haijima Kazumi,JPX, Structure and method of performing DMA transfers between memory and I/O devices utilizing a single DMA controller within.
  11. Poloniewicz Paul R. ; Biuso Anthony D. ; Buongervino Nicholas, System for converting signals into a predetermined data exchange format with plug-in modular connector having voltage, g.
  12. Costes Michel (Cagnes S/Mer FRX) Gach Alain (Vence FRX) Hartmann Yves (Vence FRX) Peyronnenc Michel (St Jeannet FRX), System with plural clocks for bidirectional information exchange between DMA controller and I/O devices via DMA bus.

이 특허를 인용한 특허 (22)

  1. Karaki, Nobuo, Asynchronous serial communication method and asynchronous serial communication device.
  2. Marston, Bert, Combo ID detection.
  3. Fish, Andrew J., Mechanism to determine trust of out-of-band management agents.
  4. Ito, Takafumi, Memory card and host device thereof.
  5. Ito, Takafumi, Memory card and host device thereof.
  6. Ito, Takafumi, Memory card and host device thereof.
  7. Ito, Takafumi, Memory card and host device thereof.
  8. Ito, Takafumi, Memory card and host device thereof.
  9. Ito, Takafumi, Memory card and host device thereof.
  10. Ito, Takafumi, Memory card and host device thereof.
  11. Reinbold,Lukas, Method and apparatus for loading configuration data.
  12. Kumar,Mohan J.; Elkhoury,Bassam N., Method and apparatus for setting timing parameters.
  13. Atkinson, Lee, Method and system of controlling transfer speed of bus transactions.
  14. Anzai, Takeshi, Parallel data transfer method and system of DDR divided data with associated transfer clock signal over three signal lines.
  15. Sutton, II, James A.; Grawrock, David W., System and method for execution of a secured environment initialization instruction.
  16. Sutton, II, James A.; Grawrock, David W., System and method for execution of a secured environment initialization instruction.
  17. Sutton, II, James A.; Grawrock, David W., System and method for execution of a secured environment initialization instruction.
  18. Sutton, II, James A.; Grawrock, David W., System and method for execution of a secured environment initialization instruction.
  19. Sutton, II, James A.; Grawrock, David W., System and method for execution of a secured environment initialization instruction.
  20. Sutton, II, James A.; Grawrock, David W., System and method for execution of a secured environment initialization instruction.
  21. Sutton, James A; Grawrock, David W, System and method for execution of a secured environment initialization instruction.
  22. Robertson, William L., System and method for hot swapping daughtercards in high availability computer systems.
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