$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Process for making a semiconductor device with barrier film formation using a metal halide and products thereof

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/441
  • H01L-021/4763
출원번호 US-0137089 (1998-08-20)
발명자 / 주소
  • Stumborg Michael F.
  • Santiago Francisco
  • Chu Tak Kin
  • Boulais Kevin A.
출원인 / 주소
  • The United States of America as represented by the Secretary of the Navy
대리인 / 주소
    Bechtel, Esq.
인용정보 피인용 횟수 : 50  인용 특허 : 32

초록

Process for making a semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, su

대표청구항

[ What is claimed is:] [1.] A process for making a semiconductor device comprising the steps of:depositing, on a surface of a substrate, a precursor comprising a metal halide compound;removing the precursor except for a layer of metal atoms retained as a monolayer immediately adjacent said surface o

이 특허에 인용된 특허 (32)

  1. Lim Sheldon C. P. (Sunnyvale CA) Chu Stanley C. (Cupertino CA), Barrier layer enhancement in metallization scheme for semiconductor device fabrication.
  2. Himpsel Franz J. (Mt. Kisco NY), Epitaxy of high TC superconductors on silicon.
  3. Nakamura Takashi (Kyoto JPX), Ferroelectric field effect transistor with fluoride buffer and IV-VI ferroelectric.
  4. Eizenberg Moshe (Kiryat-Ata NJ ILX) Murarka Shyam P. (New Providence NJ), Forming low-resistance contact to silicon.
  5. Childs Timothy T. (Minnetonka MN) Nohava Thomas (Apple Valley MN), GaAs heterostructure metal-insulator-semiconductor integrated circuit technology.
  6. Heremans Joseph P. (Troy MI) Partin Dale L. (Sterling Heights MI), Hot electron transistors.
  7. Mitchell Douglas G. ; Carney Francis J. ; Woolsey Eric J., Interconnect system and method of fabrication.
  8. Tsang Won-Tien (New Providence NJ), MOS Devices.
  9. Joshi Rajiv V. (Yorktown Heights NY) Oh Choon-Sik (Seoul CT KRX) Moy Dan (Bethel CT), MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain an.
  10. Choi Kyeong K. (Ichonshi KRX), Method for fabricating a diffusion barrier metal layer in a semiconductor device.
  11. Kim Jun K. (Seoul KRX) Lee Kyung I. (Seoul KRX), Method for forming a copper metal wiring with aluminum containing oxidation barrier.
  12. Ohba Takayuki (Yokohama JPX), Method for manufacturing semiconductor device.
  13. Joshi Rajiv V. (Yorktown Heights NY) Oh Choon-Sik (Seoul CT KRX) Moy Dan (Bethal CT), Method for selective deposition of refractory metals on silicon substrates and device formed thereby.
  14. Cho Chih-Chen, Method for the growth of epitaxial metal-insulator-metal-semiconductor structures.
  15. Summerfelt Scott R. (Dallas TX) Reid Jason (Pasadena CA) Nicolet Marc (Pasadena CA) Kolawa Elzbieta (Sierra Madre CA), Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes.
  16. Nishioka Yasushiro (Tsukuba TX JPX) Summerfelt Scott R. (Dallas TX) Park Kyung-Ho (Tsukuba JPX) Bhattacharya Pijush (Midnapur INX), Method of forming high-dielectric-constant material electrodes comprising sidewall spacers.
  17. Choi Kyeong Keun (Ichonkun KRX), Method of forming metal interconnection layer of semiconductor device.
  18. Morar John F. (Mahopac NY) Tromp Rudolf M. (Mount Kisco NY), Methods for forming epitaxial self-aligned calcium silicide contacts and structures.
  19. Milano, Raymond A., Multilayer modulation doped heterostructure charge coupled device.
  20. Huang Yuan-Chang (Hsin-Chu TWX) Chang Kuang-Hui (Hsin-Chu TWX), Post contact layer etch back process which prevents precipitate formation.
  21. McKee Rodney A. (Kingston TN) Walker Frederick J. (Oak Ridge TN), Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process.
  22. McKee Rodney A. (Kingston TN) Walker Frederick J. (Oak Ridge TN), Process for depositing epitaxial alkaline earth oxide onto a substrate and structures prepared with the process.
  23. Sun Shi-Chung (Taipei TWX) Chiu Hien-Tien (Taipei TWX) Tsai Ming-Hsing (Chiayi TWX), Process for fabricating tantalum nitride diffusion barrier for copper matallization.
  24. Gelatos Avgerinos V. (Austin TX) Fiordalice Robert W. (Austin TX), Process for forming copper interconnect structure.
  25. Santiago Francisco (Elkridge MD) Chu Tak K. (Bethesda MD) Stumborg Michael F. (Bethesda MD), Process for forming epitaxial BaF2 on GaAs.
  26. Santiago Francisco (Elkridge MD) Chu Tak-Kin (Bethesda MD) Stumborg Michael (Rockville MD), Process for forming epitaxial BaF2 on GaAs.
  27. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
  28. Clark Marion D. (11725 Montana Ave. Los Angeles CA 90049) Anderson C. Lawrence (4409 Henley Ct. Westlake Village CA 91360), Schottky barrier charge coupled device (CCD) manufacture.
  29. Chin Maw-Rong (Huntington Beach CA) Warren Gary (Huntington Beach CA) Liao Kuan-Yang (Laguna Niguel CA), Self-aligned contact diffusion barrier method.
  30. Koubuchi Yasushi (Hitachi JPX) Onuki Jin (Hitachi JPX) Koizumi Masahiro (Hitachi JPX), Semiconductor device.
  31. Lee Sang-in (Suwon KRX), Semiconductor device and method for manufacturing the same.
  32. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (50)

  1. Sneh, Ofer; Seidel, Thomas E.; Galewski, Carl, Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition.
  2. Raaijmakers,Ivo; Haukka,Suvi P.; Saanila,Yille A.; Soininen,Pekka J.; Elers,Kai Erik; Granneman,Ernst H. A., Conformal lining layers for damascene metallization.
  3. Bauer, Matthias; Thomas, Shawn G., Cyclical epitaxial deposition and etch.
  4. Todd, Michael A., Deposition of amorphous silicon-containing films.
  5. Michael F. Stumborg ; Francisco Santiago ; Tak Kin Chu ; Kevin A. Boulais, Electronic devices with a barrier film and process for making same.
  6. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Electronic devices with barium barrier film and process for making same.
  7. Stumborg, Michael F.; Santiago, Francisco; Chu, Tak Kin; Boulais, Kevin A., Electronic devices with cesium barrier film and process for making same.
  8. Tak Kin Chu ; Francisco Santiago ; Kevin A. Boulais, Electronic devices with diffusion barrier and process for making same.
  9. Bauer, Matthias, Epitaxial deposition of doped semiconductor materials.
  10. Sneh, Ofer; Seidel, Thomas E., Fully integrated process for MIM capacitors using atomic layer deposition.
  11. Bauer, Matthias, High throughput cyclical epitaxial deposition and etch process.
  12. Forehand, David, Improving back-contact performance of group VI containing solar cells by utilizing a nanoscale interfacial layer.
  13. Sneh, Ofer, Integration of ferromagnetic films with ultrathin insulating film using atomic layer deposition.
  14. Tu,Kuo Chi; Chen,Chun Yao; Wuu,Shou Gwo; Wang,Chen Jong, MIM capacitor structure and method of manufacture.
  15. Alessandra Satta BE; Karen Maex BE; Kai-Erik Elers FI; Ville Antero Saanila FI; Pekka Juha Soininen FI; Suvi P. Haukka FI, Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
  16. Satta, Alessandra; Maex, Karen; Elers, Kai-Erik; Saanila, Ville Antero; Soininen, Pekka Juha; Haukka, Suvi P., Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
  17. Satta, Alessandra; Maex, Karen; Elers, Kai-Erik; Saanila, Ville Antero; Soininen, Pekka Juha; Haukka, Suvi P., Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
  18. Raaijmakers, Ivo; Soininen, Pekka T.; Granneman, Ernst H. A.; Haukka, Suvi P., Method for controlling conformality with alternating layer deposition.
  19. Sun,Grace; Zubkov,Vladimir; Barth,William K.; Lakshminarayanan,Sethuraman; Sun,Sey Shing; Suvkhanov,Agajan; Cui,Hao, Method for creating barrier layers for copper diffusion.
  20. Zubkov, Vladimir; Aronowitz, Sheldon, Method for creating barriers for copper diffusion.
  21. Zubkov,Vladimir; Aronowitz,Sheldon, Method for creating barriers for copper diffusion.
  22. Martins Loureiro, Sergio Paulo; Venkataramani, Venkat Subramaniam; Clarke, Lucas; McEvoy, Kevin P.; Vess, Carl Joshua; McNulty, Thomas; Duclos, Steven Jude; Ivan, Adrian; Hubbard, Patricia A., Method for making sintered cubic halide scintillator material.
  23. Hau Riege,Stefan; List,R. Scott, Method of doping a conductive layer near a via.
  24. Van Nooten, Sebastian E.; Maes, Jan Willem; Marcus, Steven; Wilk, Glen; Räisänen, Petri; Elers, Kai-Erik, Method of forming non-conformal layers.
  25. Hau-Riege, Stefan; List, R. Scott, Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability.
  26. Raaijmakers, Ivo; Haukka, Suvi P.; Saanila, Ville A.; Soininen, Pekka J.; Elers, Kai-Erik; Granneman, Ernst H. A., Method of making conformal lining layers for damascene metallization.
  27. Thompson, David; Anthis, Jeffrey W., Methods of depositing a metal alloy film.
  28. Bauer, Matthias, Methods of depositing electrically active doped crystalline Si-containing films.
  29. Bauer, Matthias; Weeks, Keith Doran; Tomasini, Pierre; Cody, Nyles, Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition.
  30. Bauer,Matthias; Weeks,Keith Doran; Tomasini,Pierre; Cody,Nyles, Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition.
  31. Chen, Yong, Nanoscale electric lithography.
  32. Todd, Michael A.; Hawkins, Mark, Process for deposition of semiconductor films.
  33. Chu, Tak Kin; Santiago, Francisco; Boulais, Kevin A., Process for making electronic devices having a monolayer diffusion barrier.
  34. Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Processes for making electronic devices with rubidum barrier film.
  35. Ivo Raaijmakers NL; Pekka T. Soininen FI; Ernst H. A. Granneman NL; Suvi P. Haukka FI, Protective layers prior to alternating layer deposition.
  36. Raaijmakers, Ivo; Soininen, Pekka T.; Granneman, Ernst H. A.; Haukka, Suvi P., Protective layers prior to alternating layer deposition.
  37. Ofer Sneh, Radical-assisted sequential CVD.
  38. Raaijmakers, Ivo; Soininen, Pekka T.; Granneman, Ernst; Haukka, Suvi; Elers, Kai-Erik; Tuominen, Marko; Sprey, Hessel; Terhorst, Herbert; Hendriks, Menso, Sealing porous structures.
  39. Bauer, Matthias; Arena, Chantal; Bertram, Ronald; Tomasini, Pierre; Cody, Nyles; Brabant, Paul; Italiano, Joseph; Jacobson, Paul; Weeks, Keith Doran, Selective deposition of silicon-containing films.
  40. Bauer, Matthias; Weeks, Keith Doran, Selective epitaxial formation of semiconductive films.
  41. Bauer, Matthias; Weeks, Keith Doran, Selective epitaxial formation of semiconductor films.
  42. Cho,Gyung Su, Semiconductor device and fabrication method thereof.
  43. Shekhar Pramanick ; Takeshi Nogami, Semiconductor interconnect barrier and manufacturing method thereof.
  44. Bauer, Mathias, Separate injection of reactive species in selective formation of films.
  45. Bauer, Matthias, Separate injection of reactive species in selective formation of films.
  46. Thomas, Shawn; Tomasini, Pierre, Stressor for engineered strain on channel.
  47. Bauer, Matthias, Structure comprises an As-deposited doped single crystalline Si-containing film.
  48. Aggarwal, Ravinder; Conner, Rand; Disanto, John; Alexander, James A., Substrate reactor with adjustable injectors for mixing gases within reaction chamber.
  49. Todd, Michael A.; Raaijmakers, Ivo, Thin films and methods of making them.
  50. Edward C. Cooney, III ; Anthony K. Stamper, Ultra-thin tantalum nitride copper interconnect barrier.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트