초록 ▼

A method of designing FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configu

A method of designing FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configuration, reconfiguration and host run-time operation being supported in a single piece of code. Design compile times on the order of seconds and built-in support for parameterized cells are significant features of the inventive method.

대표청구항 ▼

[ What is claimed is:] [1.] A method of configuring a field programmable gate array (FPGA), the FPGA being connected to a host processor for configuration thereby; the method comprising the steps of:a) programming the host processor with instructions in a high level programming language;b) instantia

[ What is claimed is:] [1.] A method of configuring a field programmable gate array (FPGA), the FPGA being connected to a host processor for configuration thereby; the method comprising the steps of:a) programming the host processor with instructions in a high level programming language;b) instantiating elements from a library of elements compatible with the high level programming language;c) providing a compiler for the high level programming language to the host processor for generating executable code in response to the programmed instructions and the instantiated library elements, the executable code including compiled placement and routing information; andd) configuring the FPGA from the host processor in response to the executable code.