초록 ▼

A sample signal is sequentially transported through a plurality of serial shift registers in respective data channels. The sample signal varies between a pair of levels, namely a first level and a second level, to resemble a step with respect to time. The shift registers are monitored by a skew dete

A sample signal is sequentially transported through a plurality of serial shift registers in respective data channels. The sample signal varies between a pair of levels, namely a first level and a second level, to resemble a step with respect to time. The shift registers are monitored by a skew detection circuit to identify the shift register that receives the sample signal at the time of a generated timing signal. Data signals are then passed through the recorded shift register while compensating for detected skew in parallel transmission data.

대표청구항 ▼

[ What is claimed is:] [1.] A parallel data skew detecting circuit, comprising:a plurality of parallel data channels including a plurality of serial shift registers to transmit a sample signal;a timing signal generating circuit to generate a timing signal in a predetermined period;a skew storage cir

[ What is claimed is:] [1.] A parallel data skew detecting circuit, comprising:a plurality of parallel data channels including a plurality of serial shift registers to transmit a sample signal;a timing signal generating circuit to generate a timing signal in a predetermined period;a skew storage circuit to record the shift register which receives the sample signal for the respective data channels when the timing signal is generated; anda processing completion detecting circuit to detect that all of the data channels have received the sample signal within a skew detecting period defined by the number of the shift registers, and to output a completion signal upon completion of the detection, to thereby confirm that skew is detected.