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Semiconductor memory device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-011/24
출원번호 US-0222799 (1998-12-30)
우선권정보 JP-0045864 (1996-03-04)
발명자 / 주소
  • Morishita Fukashi,JPX
  • Tomishima Shigeki,JPX
  • Arimoto Kazutani,JPX
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha, JPX
대리인 / 주소
    McDermott, Will & Emery
인용정보 피인용 횟수 : 140  인용 특허 : 6

초록 ▼

In a dynamic random access memory, at a time of body-refresh operation, a bit-line potential VBL is set to a body-refresh-potential VBR, and the body-refresh-potential VBR is supplied to bit-line pairs via a bit-line precharging/equalizing circuit 111c, thereby the charge accumulated in the body of

대표청구항 ▼

[ We claim:] [1.] A semiconductor device comprising:an insulated gate type transistor having a source, a drain, a floating body sandwiched by the source and drain, and a gate formed above the floating body; anda charge draining circuit for draining out charge accumulated in the floating body of said

이 특허에 인용된 특허 (6)

  1. Mistry Kaizad Rumy ; Sleight Jeffrey William, Compact self-aligned body contact silicon-on-insulator transistor.
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  2. Vu Duy-Phach (Taunton MA) Cheong Ngwe K. (Boston MA), Reduction of parasitic effects in floating body mosfets.
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  3. Pelella Mario M. A. ; Assaderaghi Fariborz ; Wagner ; Jr. Lawrence Federick, SOI FET design to reduce transient bipolar current.
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  4. Yamada Toshio (Sakai JPX) Inoue Michihiro (Ikoma JPX), Seimiconductor memory device having sub bit lines.
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  6. Rose James W. (San Carlos CA) D\Souza Godfrey P. (Santa Clara CA) Stinehelfer Jonathan J. (San Jose CA) Testa James F. (Mountain View CA), Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage.
    상세보기

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