초록 ▼

A process for forming damascene wiring within an integrated circuit is described. After the trenches have been filled and planarized, normal dishing of the copper is present. This is then eliminated by depositing a layer of a chrome-copper alloy over the damascene wiring and then planarizing this la

A process for forming damascene wiring within an integrated circuit is described. After the trenches have been filled and planarized, normal dishing of the copper is present. This is then eliminated by depositing a layer of a chrome-copper alloy over the damascene wiring and then planarizing this layer so that it covers only the copper in the damascene trench. Then, while the IMD is deposited, some of the chromium in the alloy gets selectively oxidized, resulting in a self-aligned barrier layer of chromium oxide at the copper to IMD interface.

대표청구항 ▼

[ What is claimed is:] [1.] A process to self-passivate copper damascene wiring, comprising:providing a partially completed integrated circuit, including a top layer of a dielectric wherein a pattern of damascene copper wiring has been formed;depositing a layer of chrome-copper alloy on said dielect

[ What is claimed is:] [1.] A process to self-passivate copper damascene wiring, comprising:providing a partially completed integrated circuit, including a top layer of a dielectric wherein a pattern of damascene copper wiring has been formed;depositing a layer of chrome-copper alloy on said dielectric layer and damascene wiring;planarizing said layer of chrome-copper alloy thereby eliminating any dishing above the damascene wiring; anddepositing a layer of IMD on the layer of chrome-copper alloy thereby forming an interface, between the chrome-copper and the IMD, that comprises a self-aligned barrier.