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Method for increasing gate capacitance by using both high and low dielectric gate material

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/60
  • H01L-021/28
출원번호 US-0052386 (1998-03-31)
발명자 / 주소
  • Krivokapic Zoran
  • Krishnan Srinath
  • Yeap Geoffrey Choh-Fei
  • Buynoski Matthew
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Amin, Eschweiler & Turocy, LLP
인용정보 피인용 횟수 : 95  인용 특허 : 23

초록

A method for fabricating a MOSFET device is provided. The method includes a step of fining a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be o

대표청구항

[ What is claimed is:] [1.] A method for fabricating a MOSFET device including the step of:forming a gate oxide including first and second gate oxide materials, the first gate oxide material having a dielectric constant of about .epsilon.100 and a higher dielectric constant than the first gate oxide

이 특허에 인용된 특허 (23)

  1. Mishra Umesh Kumar ; Parikh Primit A., Enhancement-depletion logic based on gaas mosfets.
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