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Scalable graphics processor architecture

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/16
출원번호 US-0070162 (1998-04-30)
발명자 / 주소
  • Kelleher Brian M.
  • Dewey Thomas E.
출원인 / 주소
  • 3D Labs, Inc., GBX
대리인 / 주소
    Sawyer Law Group LLP
인용정보 피인용 횟수 : 71  인용 특허 : 7

초록

A scalable graphics processor architecture is disclosed in accordance with the present invention. In a first aspect, the architecture comprises a base graphics architecture. The architecture further includes an expansion graphic architecture, the expansion graphics architecture being mateably couple

대표청구항

[ What is claimed is:] [1.] A scalable graphics processor architecture comprising:a base graphics architecture; wherein the base graphics architecture further comprises: a plurality of rendering processors; a first bus coupled to the plurality of processors for providing I/O signals to the processor

이 특허에 인용된 특허 (7)

  1. Bright Arthur Aaron ; Kosonocky Stephen Victor ; Warren Kevin Wilson, Embedded frame buffer system and synchronization method.
  2. Shaw Venson ; Shaw Steven M., Method and apparatus including system architecture for multimedia communication.
  3. Alcorn Byron A. ; Stroyan Howard D. ; Bailey Randy L., Multiple graphics pipeline integration with a windowing system through the use of a high speed interconnect to the fram.
  4. Farrell Robert (Hillsborough NJ) Lippincott Louis (Roebling NJ), Scalable multimedia platform architecture.
  5. Kehlet David C. ; Lavelle Michael G. ; Deering Michael F., Scene synchronization of multiple computer displays.
  6. Reddy Chitranjan N., Shared memory graphics accelerator system.
  7. Sieffert Kent J. (Minneapolis MN), System for communication of image information between multiple-protocol imaging devices.

이 특허를 인용한 특허 (71)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  11. Heidari-Bateni, Ghobad; Plunkett, Robert Thomas, Adaptive, multimode rake receiver for dynamic search and multipath reception.
  12. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master,Paul L.; Smith,Stephen J.; Watson,John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  19. Kelleher, Brian M., Apparatus, system, and method for joint processing in graphics processing units.
  20. Hogenauer, Eugene B., Arithmetic node including general digital signal processing functions for an adaptive computing machine.
  21. Howard, Ric; Katragadda, Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.
  22. de Waal, Abraham B.; Diard, Franck R., Automatic quality testing of multimedia rendering by software drivers.
  23. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  24. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  25. Rubin, Owen Robert; Murray, Eric; Uhrig, Nalini Praba, Consumer product distribution in the embedded system market.
  26. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  27. Ebihara, Hitoshi, Data communication system and method, computer program, and recording medium.
  28. French, Mark J.; Keslin, Phillip; Molnar, Steven E; Weitkemper, Adam Clark, Early Z testing for multiple render targets.
  29. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  30. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  31. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  32. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  33. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  34. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  35. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  36. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  37. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  38. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James, Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements.
  39. Diamond,Michael B.; Carrera,Cesar, Housing for a scalable graphics processor.
  40. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas, Input/output controller node in an adaptable computing environment.
  41. Heidari-Bateni, Ghobad; Sambhwani, Sharad D., Internal synchronization control for adaptive integrated circuitry.
  42. French, Mark J.; Keslin, Phillip; Molnar, Steven E; Weitkemper, Adam Clark, Late Z testing for multiple render targets.
  43. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  44. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  45. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  46. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  47. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  48. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  49. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  50. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  51. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  52. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  53. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  54. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  55. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  56. Master, Paul L.; Scheuermann, W. James, Method and system for reducing the time-to-market concerns for embedded system design.
  57. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  58. Ebeling, W. H. Carl; Hogenauer, Eugene B., Method, system and software for programming reconfigurable hardware.
  59. Gonzalez, Nelson; Organvidez, Humberto, Motherboard for supporting multiple graphics cards.
  60. Kelleher, Brian M., Multi-chip graphics processing unit apparatus, system, and method.
  61. Gonzalez, Nelson; Organvidez, Humberto; Cabello, Ernesto; Organvidez, Juan H., Multiple parallel processor computer graphics system.
  62. Gonzalez,Nelson; Organvidez,Humberto; Cabello,Ernesto; Organvidez,Juan H., Multiple parallel processor computer graphics system.
  63. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.
  64. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  65. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas, Secure storage of program code for an embedded system.
  66. Master,Paul L.; Watson,John, Storage and delivery of device features.
  67. Jacob,Rojit; Chuang,Dan Minglun, System and method using embedded microprocessor as a node in an adaptable computing machine.
  68. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  69. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  70. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  71. French, Mark J.; Keslin, Phillip; Molnar, Steven E; Weitkemper, Adam Clark, Z-test result reconciliation with multiple partitions.
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