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Method of forming shallow trench isolation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/76
출원번호 US-0286354 (1999-04-05)
발명자 / 주소
  • Tseng Horng-Huei,TWX
출원인 / 주소
  • Vanguard International Semiconductor Corp., TWX
대리인 / 주소
    Patents
인용정보 피인용 횟수 : 79  인용 특허 : 6

초록

A method of fabricating a shallow trench isolation. A pad oxide and a dielectric layer are formed on a substrate. A trench is formed in the substrate penetrating through the pad oxide layer and the dielectric layer. The dielectric layer around the edge of the trench is removed to expose the substrat

대표청구항

[ What is claimed is:] [13.] A method of forming a shallow trench isolation, comprising:providing a substrate;sequentially forming a pad oxide layer and a dielectric layer on the substrate;removing a part of the pad oxide layer, the dielectric layer and the substrate to form a trench with a first de

이 특허에 인용된 특허 (6)

  1. Hsueh Cheng-Chen Calvin,TWX ; Yen Chu-Tsao, Isolation trenches with protected corners.
  2. Kuo Chien-Li,TWX, Method for manufacturing shallow trench isolation.
  3. Lan Shih-Ming,TWX, Method of fabricating shallow trench isolation.
  4. Jin Joo-hyun,KRX ; Shin Yun-seung,KRX, Methods of forming trench isolation regions using repatterned trench masks.
  5. Werner Thomas ; Dawson Robert, Process for forming an isolation region with trench cap.
  6. Saki Kazuo,JPX, Shallow trench isolation structure and method of forming the same.

이 특허를 인용한 특허 (79)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
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  4. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  5. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  6. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  30. Doris, Bruce B.; Gluschenkov, Oleg; Zhang, Ying; Zhu, Huilong, Method for forming a multi-gate device with high k dielectric for channel top surface.
  31. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
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  33. Akira Mitsuiki JP, Method of forming a shallow trench isolation structure in a semiconductor device.
  34. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
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  36. Moore, John T.; Blalock, Guy T., Methods of forming materials within openings, and methods of forming isolation regions.
  37. Tseng Horng-Huei,TWX, Methods of forming trench isolation regions using spin-on material.
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  39. Doris,Bruce B.; Gluschenkov,Oleg; Zhang,Ying; Zhu,Huilong, Multi-gate device with high k dielectric for channel top surface.
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  43. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  48. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  75. Zhu,Hiulong; Bedell,Steven W.; Doris,Bruce B.; Zhang,Ying, Structures and methods for making strained MOSFETs.
  76. Aquilino, Michael V.; Vega, Reinaldo A., Trench isolation structure.
  77. Aquilino, Michael V.; Vega, Reinaldo A., Trench isolation structure.
  78. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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