초록 ▼

The present invention pertains to an apparatus and method for transparently coupling PCI devices behind a PCI-to-PCI bridge. A controller is coupled to a primary PCI bus and includes a secondary PCI bus that is coupled to the primary PCI bus by a PCI-to-PCI bridge. The secondary PCI bus includes a n

The present invention pertains to an apparatus and method for transparently coupling PCI devices behind a PCI-to-PCI bridge. A controller is coupled to a primary PCI bus and includes a secondary PCI bus that is coupled to the primary PCI bus by a PCI-to-PCI bridge. The secondary PCI bus includes a number of exposed PCI devices that are recognizable by the bridge and a number of hidden PCI devices that are hidden from the bridge. A bridge assist device (BASS) is one such exposed PCI device that is used to acquire a memory address space that is part of the system memory. The memory address space is then partitioned by the controller and assigned to each of the hidden PCI devices. The hidden PCI devices use the memory address space to transmit data to the local CPU. The controller also includes a local-to-PCI bridge that is coupled to the secondary PCI bus and a local bus including a memory and a processor. The local-to-PCI bridge acquires a second memory address space that is part of the system memory and which is used to transmit data between the hidden PCI devices and a local memory.

대표청구항 ▼

[ What is claimed is:] [1.] A data processing system, comprising:a host computer comprising a first processor and a system memory comprising a plurality of memory address spaces, the system memory under the control of the first processor;a first bus in communication with the first processor and the

[ What is claimed is:] [1.] A data processing system, comprising:a host computer comprising a first processor and a system memory comprising a plurality of memory address spaces, the system memory under the control of the first processor;a first bus in communication with the first processor and the system memory;a controller connected to the first bus comprising a second processor; and, a second bus connected to a plurality of VO devices and the controller, each of the I/O devices associated with a select portion of a first memory address space of the system memory, the first memory address space under the control of the second processor, the first memory address space used by each of the I/O devices to communicate with the second processor.