초록 ▼

A real time digital systolic processor with a core of reconfigurable interconnected macrocells which can be programmed according to function for processing high bandwidth digital data. Each macrocell contains arithmetic logic units for performing predetermined functions based on format of the input

A real time digital systolic processor with a core of reconfigurable interconnected macrocells which can be programmed according to function for processing high bandwidth digital data. Each macrocell contains arithmetic logic units for performing predetermined functions based on format of the input data stream from an outside source or from other macrocells. The interconnects between each macrocell are arranged so that the function of the device is predetermined according to user specific applications.

대표청구항 ▼

[ What is claimed:] [21.] An integrated circuit for processing a plurality of multiple-bit data signals, comprising:a plurality of input terminals for receiving respective ones of the data signals;a plurality of output terminals;a variable delay buffer coupled to the input terminals for receiving th

[ What is claimed:] [21.] An integrated circuit for processing a plurality of multiple-bit data signals, comprising:a plurality of input terminals for receiving respective ones of the data signals;a plurality of output terminals;a variable delay buffer coupled to the input terminals for receiving the data signals; andlogic circuitry coupled to the variable delay buffer for selectively delaying the data signals to equalize the data signals in time with respect to each other, thereby producing equalized data signals, the output terminals coupled to the variable delay buffer for presenting the equalized data signals.