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Semiconductor chip carrier including an interconnect component interface 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0244435 (1999-02-04)
발명자 / 주소
  • Crane
  • Jr. Stanford W.
  • Portuondo Maria M.
출원인 / 주소
  • Silicon Bandwidth, Inc.
대리인 / 주소
    Morgan, Lewis, & Bockius LLP
인용정보 피인용 횟수 : 9  인용 특허 : 52

초록

A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of eac

대표청구항

[ What is claimed is:] [1.] A semiconductor die carrier comprising:a semiconductor die;a die carrier housing comprising an interior space for receiving said semiconductor die;a plurality of electrically-conductive leads extending through said die carrier housing, each of said plurality of leads comp

이 특허에 인용된 특허 (52)

  1. Kardos Gabor (Sunnyvale CA), Adapter which emulates ball grid array packages.
  2. Frei John K. (Mesa AZ) Brice-Heames Kenneth (Mesa AZ), Apparatus for adapting semiconductor die pads and method therefor.
  3. Murphy James V. (Warwick RI) Murphy Michael J. (East Greenwich RI) Fisher Burton (Coventry RI) Taylor Robert (Coventry RI), Ball grid array socket assembly.
  4. Higgins ; III Leo M. (Lakeville MA), Circuit board fabrication.
  5. Sucheski Matthew M. (Harrisburg PA) Barkus Lee A. (Millersburg PA), Coaxial contact element.
  6. Kanai Yasunori (Inagi JPX), Connection lead arrangement for a semiconductor device.
  7. Abe Shunji (Yokohama JPX) Uratsuji Kazumi (Tokyo JPX), Contact structure for IC socket.
  8. Johnson David A. (St. Louis Park MN), Contacting system for electrical devices.
  9. Johnson David A. (Wayzata MN) Kline Eric V. (Stillwater MN), Contacting system for electrical devices.
  10. Goldfarb Samuel (21 Sycamore Dr. Roslyn ; County of Nassau NY 11576), Electronic component package with multiconductive base forms for multichannel mounting.
  11. Bearinger Clayton R. (Midland MI) Camilletti Robert C. (Midland MI) Kilby Jack S. (Dallas TX) Haluska Loren A. (Midland MI) Michael Keith W. (Midland MI), Flip chip silicone pressure sensitive conductive adhesive.
  12. Sugimoto Masahiro (Yokosuka JPX) Wakasugi Yasumasa (Kawasaki JPX) Harada Shigeki (Kawasaki JPX), Heatsink package for flip-chip IC.
  13. Shaheen Joseph M. (La Habra CA) Yamaguchi James S. (Lake Forest CA), Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture.
  14. Chillara Satya (San Jose CA) Mostafazadeh Shahram (San Jose CA), High density integrated circuit assembly combining leadframe leads with conductive traces.
  15. Frankeny, Jerome A.; Frankeny, Richard F.; Haj-Ali-Ahmadi, Javad; Hermann, Karl; Imken, Ronald L., High density interconnect strip.
  16. Manteghi Kamran, High density leaded ball-grid array package.
  17. Desai Kishor V. (Vestal NY) Macek Thomas G. (Endicott NY) Patel Maganlal S. (Endicott NY) Thomas Edwin L. (Apalachin NY), High density, separable connector and contact for use therein.
  18. Pope Richard A. (Austin TX) Boling Clyde W. (Austin TX) Bates David A. (Cedar Park TX), High-density connector.
  19. Crane ; Jr. Stanford W. (3934 NW. 57th St. Boca Raton FL 33496), High-density electrical interconnect system.
  20. Crane ; Jr. Stanford W. (3934 NW. 57th St. Boca Raton FL 33496), High-density electrical interconnect system.
  21. Crane ; Jr. Stanford W. (3934 NW. 57th St. Boca Raton FL 33496), High-density electrical interconnect system.
  22. Volfson David (Worcester MA) Senturia Stephen D. (Boston MA), High-density, multi-level interconnects, flex circuits, and tape for tab.
  23. Tukamoto Takashi (Suwa JPX) Abe Sachiyuki (Suwa JPX) Yabushita Tetsuo (Suwa JPX) Hayashi Yoshimitsu (Suwa JPX), Integrated circuit package for flexible computer system alternative architectures.
  24. Lin Paul T. (Austin TX), Leaded semiconductor device having accessible power supply pad terminals.
  25. Swamy Deepak (Austin TX) Pecone Victor (Austin TX), Leadless high density connector.
  26. Shaffer Howard R. (Millersburg PA), Limited insertion force contact terminals and connectors.
  27. Keglewitsch Josef (Addison IL) Vladic Daniel P. (Berwyn IL), Low cost electrical connector.
  28. Mosley Joseph M. ; Portuondo Maria M. ; Taylor Drew L., Low profile semiconductor die carrier.
  29. Gregoire George D. (9927 Aviary Dr. San Diego CA 92131), Method and apparatus for making printed circuit boards.
  30. Gregoire George D. (9927 Aviary Dr. San Diego CA 92131), Method for making printed circuit boards.
  31. Collot Philippe (Orsay FRX) Schmidt Paul (Bourg la Reine FRX), Method for the self-alignment of metal contacts on a semiconductor device, and self-aligned semiconductors.
  32. Gregoire George D. (San Diego CA), Method of mounting a surface-mountable IC to a converter board.
  33. Hsu David S. Y. (Alexandria VA), Method of nanometer lithography.
  34. Reylek Robert S. (St. Paul MN) Thompson Kenneth C. (St. Paul MN), Miniature multiple conductor electrical connector.
  35. Taniuchi Kenjiro (Kawasaki JPX) Miyazawa Hideo (Kawasaki JPX) Ishikawa Kouji (Kawasaki JPX) Watanabe Kouji (Kawasaki JPX), Mounting device for mounting an electronic device on a substrate by the surface mounting technology.
  36. Martens John D. (Plano TX) Ammon J. Preston (Dallas TX), Multi row high density connector.
  37. Feng Bai-Cwo (Tarrytown NY) Feng George C. (Fishkill NY) McMaster Richard H. (Wappingers Falls NY), Multi-layer package incorporating a recessed cavity for a semiconductor chip.
  38. Koepke Richard A. (New Bedford MA), Multi-path feed-thru lead and method for formation thereof.
  39. Hirano Naohiko (Yokohama JPX), Multilayer package.
  40. Tillotson John (Southfield MI), Multiple contact header assembly.
  41. Buck Jonathan E. (Harrisburg PA) Rose William H. (Harrisburg PA), Paired contact electrical connector system.
  42. Shirling David J. (Waterbury CT), Pin grid array having seperate posts and socket contacts.
  43. Ammon J. Preston (Dallas TX) Weaver Harry R. (Dallas TX) Evans Evan J. (Plano TX), Printed circuit board finger connector.
  44. Cnyrim Henner (Laatzen DEX) Felsen Peter (Wennigsen DEX), Printed circuit board for carrying a mixed-component assembly.
  45. Brown Candice H. (San Jose CA), Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit la.
  46. Arima Hideo (Yokohama JPX) Takeda Kenji (Kamakura JPX) Yamamura Hideho (Yokohama JPX) Kobayashi Fumiyuki (Sagamihara JPX), Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same mo.
  47. Lee James C. K. (Los Altos CA) Amdahl Gene M. (Atherton CA) Amdahl Carlton G. (Saratoga CA) Beck Richard L. (Cupertino CA), Semiconductor chip module interconnection system.
  48. Sugimoto Masahiro (Yokosuka JPX) Wakabayashi Tetsushi (Yokohama JPX) Muratake Kiyoshi (Kawasaki JPX), Semiconductor device.
  49. Jurista Thomas M. (Vestal NY) Mantilla Osvaldo A. (Endicott NY), Sequential Connecting device.
  50. Juskey Frank J. (Coral Springs FL) Suppelsa Anthony B. (Coral Springs FL), Thermally conductive integrated circuit package with radio frequency shielding.
  51. Farnsworth Jeffery A. (Scottsdale AZ) Harper Patrick H. (Phoenix AZ) Hooley Robert (Phoenix AZ), Top loading test socket for ball grid arrays.
  52. Love David G. (Pleasanton CA) Moresco Larry L. (San Carlos CA) Chou William Tai-Hua (Cupertino CA) Horine David A. (Los Altos CA) Wong Connie M. (Fremont CA) Beilin Solomon I. (San Carlos CA), Wire interconnect structures for connecting an integrated circuit to a substrate.

이 특허를 인용한 특허 (9)

  1. Kim, Tae Jun; Song, Yoo Sun, Chip on board package for optical mice and lens cover for the same.
  2. Moran, Dov, Electronic module with dual connectivity.
  3. Moran,Dov, Electronic module with dual connectivity.
  4. Conn, Robert O., Integral metal structure with conductive post portions.
  5. Engle,Jason; Abrio,Rhandee; Bradbury Bennett,Julie Roslyn; Allee,Greg; Kledzik,Kenneth, Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips.
  6. Crane, Jr., Stanford W.; Portuondo, Maria M., Semiconductor chip carrier affording a high-density external interface.
  7. Crane, Jr.,Stanford W.; Portuondo,Maria M., Semiconductor chip carrier affording a high-density external interface.
  8. Gates, Tim M.; Stone, Brent S., Semiconductor package having multi-signal bus bars.
  9. Gates,Tim M.; Stone,Brent S., Semiconductor package having multi-signal bus bars.
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