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Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/00
  • H05K-001/14
  • H01L-023/12
  • H01L-023/52
출원번호 US-0237840 (1999-01-27)
우선권정보 JP-0375342 (1998-12-14)
발명자 / 주소
  • Gaku Morio,JPX
  • Ikeguchi Nobuyuki,JPX
  • Kobayashi Toshihiko,JPX
출원인 / 주소
  • Mitsubishi Gas Chemical Company, Inc., JPX
대리인 / 주소
    Wenderoth, Lind & Ponack, L.L.P.
인용정보 피인용 횟수 : 73  인용 특허 : 11

초록

There is provided a semiconductor plastic package in the form in which at least one semiconductor chip is mounted on a small-sized printed wiring board, a metal plate for the above package and a method of producing a copper-clad board for the above package. More particularly, there is provided a sem

대표청구항

[ What is claimed is:] [1.] A semiconductor plastic package having a structure in which a metal sheet having a size nearly equal to the size of a printed wiring board is disposed nearly in the middle of the thickness direction of the printed wiring board, at least one semiconductor chip is fixed on

이 특허에 인용된 특허 (11)

  1. Barrow Michael, Ball grid array integrated circuit package that has vias located within the solder pads of a package.
  2. Shim Il Kwon,KRX ; Heo Young Wook,KRX, Ball grid array semiconductor package with ring-type heat sink.
  3. Bodo Peter,SEX ; Hesselbom Hjalmar,SEX ; Hentzell Hans,SEX, Flip-chip type connection with elastic contacts.
  4. Patchen Lyle E. (12072 Butternut St. NW. ; Minneapolis MN 55448), Heat dissipative means for integrated circuit chip package.
  5. Vasquez Barbara (Austin TX) Stafford John W. (Phoenix AZ) Williams William M. (Gilbert AZ), Integrated circuit testing board having constrained thermal expansion characteristics.
  6. Forehand Douglas W. ; Lamoreaux Ray, Optimized routing scheme for an integrated circuit/printed circuit board.
  7. Chao Chien-Chi (Taipei TWX) Lin Ming-Hane (Chu-Pei TWX) Ho Ted C. (Hsinchu TWX), Packaging assembly with consolidated common voltage connections for integrated circuits.
  8. Takeda Shinji,JPX, Resin-sealed type ball grid array IC package and manufacturing method thereof.
  9. Inoue Kazuaki,JPX ; Yamashita Hiroyuki,JPX ; Nakamura Norio,JPX ; Yoda Hiroyuki,JPX, Semiconductor device for heat discharge.
  10. Ommen Denise M. (Phoenix AZ) Tsai Chi-Taou (Chandler AZ) Baird John (Scottsdale AZ), Semiconductor package capable of spreading heat.
  11. Mundinger David C. (Dublin CA) Scifres Donald R. (San Jose CA), Waste heat removal system.

이 특허를 인용한 특허 (73)

  1. James, Stephen L.; Rumsey, Brad D., Apparatus and method for reducing interposer compression during molding process.
  2. James, Stephen L.; Rumsey, Brad D., Apparatus and method for reducing interposer compression during molding process.
  3. Cheng, Johnny; Hsu, Joyce, BGA substrate via structure.
  4. Cheng,Johnny; Hsu,Joyce, BGA substrate via structure.
  5. Johnny Cheng TW; Joyce Hsu TW, BGA substrate via structure.
  6. Hidenori Kimbara JP; Nobuyuki Ikeguchi JP; Katsuji Komatsu JP, Ball grid array type printed wiring board having exellent heat diffusibility and printed wiring board.
  7. Harun,Fuaida; Koh,Liang Jen; Tan,Lan Chu, Bonding pad for a packaged integrated circuit.
  8. Lars-Anders Olofsson SE, Capsule for at least one high power transistor chip for high frequencies.
  9. Mishiro,Kinuko, Component mounting substrate and structure.
  10. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  11. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  12. Yatsu,Hiroyuki; Suzuki,Nobuyuki, Electronic circuit unit and method of fabricating the same.
  13. Yokozuka, Takehide; Harada, Masahide; Yamashita, Shiro; Uchiyama, Kaoru; Eguchi, Shuji; Asano, Masahiko; Sato, Koji, Electronic device.
  14. Huemoeller, Ronald P.; Rusli, Sukianto; Hiner, David Jon, Embedded electronic component package fabrication method.
  15. Kajiwara, Ryoichi; Koizumi, Masahiro; Morita, Toshiaki; Takahashi, Kazuya; Nishimura, Asao; Shinoda, Masayoshi, Flip chip assembly structure for semiconductor device and method of assembling therefor.
  16. Villanueva, Robbie U.; Dadkhah, Mahyar S.; Hashemi, Hassan S., Flip-chip leadframe package.
  17. Lee, Chang Deok; Na, Do Hyun, Increased I/O semiconductor package and method of making same.
  18. Celaya,Phillip C.; Donley,James S.; St. Germain,Stephen C., Lead-free integrated circuit package structure.
  19. Hashemi Hassan S., Leadless chip carrier design and structure.
  20. Hashemi, Hassan S., Leadless chip carrier design and structure.
  21. Megahed, Mohamed; Hashemi, Hassan S., Leadless chip carrier with embedded inductor.
  22. Hashemi, Hassan S., Leadless flip chip carrier design and structure.
  23. Brophy,Brenor L., Low cost thermally enhanced semiconductor package.
  24. Horng, Ching Fu; Wang, Yung Hui, Manufacturing method of a multi-layer circuit board embedded with a passive component.
  25. Guzek, John; Wood, Dustin, Metal core integrated circuit package with electrically isolated regions and associated methods.
  26. Kim, Nam-Jin; Ahn, Young-Cheol; Kim, Won-Jae, Method for fabricating printed circuit board.
  27. Kwok Keung Paul Ho SG; Simon Chooi SG; Yi Xu SG; Mei Sheng Zhou SG; Yakub Aliyu SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of copper solution in flip-chip, COB, and micrometal bonding.
  28. Akira Takashima JP; Kazuya Kamimura JP; Yoshikazu Kumagaya JP, Method of forming a BGA-type semiconductor device having reliable electrical connection for solder balls.
  29. Robert H. Frantz ; Ramon E. Helms, Method of manufacture for embedded processing subsystem module.
  30. Ayala, Stephane; Furter, Urs; Pellanda, Laurent, Method of manufacturing a functional inlay.
  31. Gao, Shan; Choi, Seog Moon; Kim, Tae Hyun; Hong, Ju Pyo; Jang, Bum Sik; Park, Ji Hyun, Power semiconductor module and method of manufacturing the same.
  32. Gao, Shan; Choi, Seog Moon; Kim, Tae Hyun; Hong, Ju Pyo; Jang, Bum Sik; Park, Ji Hyun, Power semiconductor module and method of manufacturing the same.
  33. Mishima,Hiroyuki; Isozaki,Tsuyoshi; Kimbara,Hidenori; Nagai,Norio, Prepreg and laminate.
  34. Lee,Sung Gue; Kim,Yong Il, Printed circuit board with a heat dissipation element and package comprising the printed circuit board.
  35. Lee, Sung Gue; Kim, Yong Il, Printed circuit board with a heat dissipation element, method for manufacturing the printed circuit board, and package comprising the printed circuit board.
  36. Hidenori Kimbara JP; Nobuyuki Ikeguchi JP; Katsuji Komatsu JP, Printed wiring board for semiconductor plastic package.
  37. Hidenori Kimbara JP; Nobuyuki Ikeguchi JP; Katsuji Komatsu JP, Printed wiring board for semiconductor plastic package.
  38. Hasebe, Keiichi; Shika, Seiji; Kashima, Naoki; Mabuchi, Yoshinori, Resin composition for printed wiring board material, and prepreg, resin sheet, metal foil clad laminate, and printed wiring board using same.
  39. Ernst, Georg; Zeiler, Thomas, Semiconductor component having a chip carrier with openings for making contact.
  40. Huang, Tien-hao; Wu, Shang-Yi; Wu, Yi-chun, Semiconductor construction, semiconductor unit, and manufacturing method thereof.
  41. Asano, Masahiko; Akutsu, Yasuo; Harada, Masahide; Uchiyama, Kaoru; Fujiwara, Shinichi; Yoshida, Isamu, Semiconductor device and electronic control unit using the same.
  42. Takeda, Shinji; Masuko, Takashi; Yusa, Masami; Kikuchi, Tooru; Miyadera, Yasuo; Maekawa, Iwao; Yamasaki, Mitsuo; Kageyama, Akira; Kaneda, Aizou, Semiconductor device and process for fabrication thereof.
  43. Takeda, Shinji; Masuko, Takashi; Yusa, Masami; Kikuchi, Tooru; Miyadera, Yasuo; Maekawa, Iwao; Yamasaki, Mitsuo; Kageyama, Akira; Kaneda, Aizou, Semiconductor device and process for fabrication thereof.
  44. Takeda, Shinji; Masuko, Takashi; Yusa, Masami; Kikuchi, Tooru; Miyadera, Yasuo; Maekawa, Iwao; Yamasaki, Mitsuo; Kageyama, Akira; Kaneda, Aizou, Semiconductor device and process for fabrication thereof.
  45. Takeda,Shinji; Masuko,Takashi; Yusa,Masami; Kikuchi,Tooru; Miyadera,Yasuo; Maekawa,Iwao; Yamasaki,Mitsuo; Kageyama,Akira; Kaneda,Aizou, Semiconductor device and process for fabrication thereof.
  46. Takeda,Shinji; Masuko,Takashi; Yusa,Masami; Kikuchi,Tooru; Miyadera,Yasuo; Maekawa,Iwao; Yamasaki,Mitsuo; Kageyama,Akira; Kaneda,Aizou, Semiconductor device and process for fabrication thereof.
  47. Takeda,Shinji; Masuko,Takashi; Yusa,Masami; Kikuchi,Tooru; Miyadera,Yasuo; Maekawa,Iwao; Yamasaki,Mitsuo; Kageyama,Akira; Kaneda,Aizou, Semiconductor device and process for fabrication thereof.
  48. Takeda,Shinji; Masuko,Takashi; Yusa,Masami; Kikuchi,Tooru; Miyadera,Yasuo; Maekawa,Iwao; Yamasaki,Mitsuo; Kageyama,Akira; Kaneda,Aizou, Semiconductor device and process for fabrication thereof.
  49. Nakazawa, Taibo; Kimura, Hiroyuki, Semiconductor device in which a semiconductor chip mounted on a printed circuit is sealed with a molded resin.
  50. Desai Kishor V. ; Patel Sunil ; Ranganathan Ramaswamy, Semiconductor flip chip ball grid array package.
  51. Shin,Won Sun; Chun,Do Sung; Lee,Sang Ho; Lee,Seon Goo; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  52. Shin, WonSun; Chun, DoSung; Lee, SangHo; Lee, SeonGoo; DiCaprio, Vincent, Semiconductor package having semiconductor chip within central aperture of substrate.
  53. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
  54. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
  55. Chien-ping Huang TW; Cheng-Yuan Lai TW; Tzu-Yi Tien TW; Chih-Ming Huang TW, Semiconductor package with a heat sink.
  56. Gaku, Morio; Ikeguchi, Nobuyuki; Yamane, Nobuyuki, Semiconductor plastic package and process for the production thereof.
  57. Morio Gaku JP; Nobuyuki Ikeguchi JP; Nobuyuki Yamane JP, Semiconductor plastic package and process for the production thereof.
  58. Kuramoto,Takeo; Tsuruta,Kaichi, Solder ball assembly for bump formation and method for its manufacture.
  59. Shin,WonSun; Chun,DoSung; Lee,SangHo; Lee,SeonGoo; DiCaprio,Vincent, Stackable semiconductor package having semiconductor chip within central through hole of substrate.
  60. Hashemi, Hassan S.; Cote, Kevin, Structure and method for fabrication of a leadless chip carrier.
  61. Coccioli, Roberto; Megahed, Mohamed; Hashemi, Hassan S., Structure and method for fabrication of a leadless chip carrier with embedded antenna.
  62. Hashemi, Hassan S.; Cote, Kevin J., Structure and method for fabrication of a leadless multi-die carrier.
  63. Kazama,Toshio; Imuta,Shogo, Support member assembly for electroconductive contact members.
  64. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  65. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  66. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  68. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  69. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  70. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  71. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  72. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
  73. Kurita, Kentaro, Wiring board, electronic component device, method for manufacturing wiring board, and method for manufacturing electronic component device.
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