초록 ▼

Methods and circuitry for implementing output buffers with low voltage CMOS transistors capable of handling signal overshoot and undershoot conditions. The circuit detects the level of the signal at an external terminal and adjusts the voltage at the gate terminals of the output transistors connecti

Methods and circuitry for implementing output buffers with low voltage CMOS transistors capable of handling signal overshoot and undershoot conditions. The circuit detects the level of the signal at an external terminal and adjusts the voltage at the gate terminals of the output transistors connecting to the external terminal in response thereto, such that oxide stress conditions are alleviated.

대표청구항 ▼

[ What is claimed is:] [7.] An output buffer circuit comprising:an n-channel pull-down transistor having a first source/drain terminal coupled to an output terminal, a second source/drain terminal coupled to a logic low power supply terminal, and a gate terminal;a feedback circuit coupled between th

[ What is claimed is:] [7.] An output buffer circuit comprising:an n-channel pull-down transistor having a first source/drain terminal coupled to an output terminal, a second source/drain terminal coupled to a logic low power supply terminal, and a gate terminal;a feedback circuit coupled between the output terminal and the gate terminal of the n-channel pull-down transistor,wherein, the feedback circuit protects the n-channel pull-down transistor against voltage stress conditions by coupling a signal at the output terminal to the gate terminal of the n-channel pull-down transistor when the signal crosses a predetermined voltage level in a first direction; anda pull-down resistive element coupling the gate terminal of the n-channel pull-down transistor to the logic low power supply terminal.