$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Fitting for incremental compilation of electronic designs 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0958436 (1997-10-27)
발명자 / 주소
  • Tse John
  • Lee Fung Fung
  • Mendel David Wolk
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Beyer Weaver & Thomas, LLP
인용정보 피인용 횟수 : 42  인용 특허 : 32

초록

If this fails, the compiler allows logic cells from the unchanged portion of the changed electronic design to shift by a limited amount to other logic elements within the target hardware device. At first, this shifting is fairly constrained in order to preserve as much of the original compilation's

대표청구항

[ What is claimed is:] [1.] In a compiler for fitting electronic designs on target hardware devices, which devices have multiple levels of hierarchical containment together defining placement of logic from the electronic designs onto the target hardware devices, a method of fitting a changed electro

이 특허에 인용된 특허 (32)

  1. Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with wire length driven affinity system.
  2. Hong Merit, Automated method for adding attributes indentified on a schematic diagram to an integrated circuit layout.
  3. Lazansky Richard W. (Pleasanton CA) Miller Thomas R. (Palo Alto CA) Coelho David R. (Fremont CA) Scott Kenneth E. (Fremont CA) Stanculescu Alec G. (San Mateo CA), Computer-aided engineering.
  4. Jones Edwin (Sunnyvale CA) Kong Soon (San Jose CA) Eirikkson Asgeir Th. (Los Gatos CA), Concurrently operating design tools in an electronic computer aided design system.
  5. Chesebro Donald G. (Colchester VT) Kim Young O. (Santa Clara County CA) Lavin Mark A. (Westchester County NY) Maynard Daniel N. (Orleans County VT), Efficient generation of fill shapes for chips and packages.
  6. Iwata Masatake (Kawasaki JPX) Kurabe Jun (Kawasaki JPX) Ichiji Hiroshi (Kawasaki JPX), Graphical user interface editing system.
  7. Stepczyk Frank M. ; Materna Anthony T. ; Hays Boyd, Graphical user interface for creating database integration specifications.
  8. Mittal Manmohan (Thousand Oaks CA), Hierarchical netlist extraction tool.
  9. Trimberger Stephen M. (San Jose CA), Hierarchical programming of electrically configurable integrated circuits.
  10. Drumm Anthony D. (Rochester MN), Incremental logic synthesis system for efficient revision of logic circuit designs.
  11. Tokunoh Seiji,JPX ; Nishiyama Tamotsu,JPX ; Tsubata Shintaro,JPX, LSI Automated design system.
  12. Trimberger Stephen M. (San Jose CA) Chene Mon-Ren (Cupertino CA), Logic placement using positionally asymmetrical partitioning method.
  13. Geer Terry L. (Baltimore OH), Mechanism for expediting the deposit, transport and submission of checks into the payment system.
  14. Drumm Anthony DeGroff, Method and apparatus for automatic post-layout optimization of an integrated circuit.
  15. Parlour David B., Method and apparatus for making incremental changes to an integrated circuit design.
  16. Sato Kenichi,JPX ; Shirota Norihisa,JPX ; Iida Yasuhiro,JPX ; Sasano Mitsuru,JPX, Method and apparatus for the design of a circuit.
  17. Rostoker Michael D. (Boulder Creek CA) Dangelo Carlos (Los Gatos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
  18. Dangelo Carlos ; Nagasamy Vijay ; Ponukumati Vijayanand, Method and system for creating and validating low-level description of electronic design.
  19. Duncan Robert G. (Castroville CA), Method for entering state flow diagrams using schematic editor programs.
  20. Knapp Steven K. (Santa Clara CA) Seidel Jorge P. (San Jose CA) Kelem Steven H. (Los Altos Hills CA), Method for generating logic modules from a high level block diagram.
  21. Freidin Philip M. (Sunnyvale CA), Method for providing multiple function symbols.
  22. Mendel David W. (Menlo Park CA), Methods for allocating circuit elements between circuit groups.
  23. Lee Jan Young, Methods for implementing circuit designs in physical circuits.
  24. Nosenchuck Daniel M. (Mercerville NJ), Optimizing compiler for computers.
  25. Shackleford J. Barry,JPX ; Yasuda Mitsuhiro,JPX ; Okushi Etsuko,JPX, Processor synthesis system and processor synthesis method.
  26. Cliff Richard G. (Milpitas CA) Cope L. Todd (San Jose CA) McClintock Cameron R. (Mountain View CA) Leong William (San Fransisco CA) Watson James A. (Santa Clara CA) Huang Joseph (San Jose CA) Ahanin , Programmable logic array integrated circuits.
  27. Kazarian Peter J. (Cupertino CA) Pedersen Bruce B. (San Jose CA) Heile Francis B. (Santa Clara CA) Mendel David Wolk (Sunnyvale CA), Routing connections for programmable logic array integrated circuits.
  28. Joshi Rajiv Vasant ; Joshi Suchitra Rajiv, Rule-based method for designing user interfaces for applications.
  29. Rostoker Michael D. ; Watkins Daniel R., System and method for creating and validating structural description of electronic system from higher-level and behavior.
  30. Heavlin William D., System and method for designing, fabricating and testing multiple cell test structures to validate a cell library.
  31. Gupte Vilas V. ; Adkar Sanjay, System simulation for testing integrated circuit models.
  32. Van Den Bout David E. (Apex NC) Tredennick Harry L. (Los Gatos CA), Universal reconfigurable printed circuit board.

이 특허를 인용한 특허 (42)

  1. Baldwin David P., Automated design system for digital circuits.
  2. Antony, George; Berry, Christopher J.; Nigaglioni, Ricardo H.; Rangarajan, Sridhar H.; Saha, Sourav; Singh, Vinay K., Critical region identification.
  3. Antony, George; Berry, Christopher J.; Nigaglioni, Ricardo H.; Rangarajan, Sridhar H.; Saha, Sourav; Singh, Vinay K., Critical region identification.
  4. Antony, George; Berry, Christopher J.; Nigaglioni, Ricardo H.; Rangarajan, Sridhar H.; Saha, Sourav; Singh, Vinay K., Critical region identification.
  5. Heile Francis B. ; Fairbanks Brent A., Incremental compilation of electronic design for work group.
  6. Gitu Jain ; Soren T. Soe, Incremental logic synthesis system for revisions of logic circuit designs.
  7. Huang Yen-Son ; Lu Martin,TWX ; Lee Chia-Huei ; Tsai Jensen, Incremental simulation using previous simulation results and knowledge of changes to simulation model to achieve fast simulation time.
  8. Fang,Hsin Wo; Ho,Ming Jing, Input/output circuits with programmable option and related method.
  9. Leaver Andrew ; Heile Francis B., Mapping heterogeneous logic elements in a programmable logic device.
  10. Ochotta, Emil S.; Stiehl, William W.; Shiflet, Eric M.; Leavesley, III, W. Story, Method and apparatus for circuit design closure using partitions.
  11. Zhuang,Nan, Method and apparatus for optimizing a logic network in a digital circuit.
  12. Van Antwerpen, Babette; Baeckler, Gregg William, Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement.
  13. Padalia, Ketan; Fung, Ryan, Method and apparatus for performing efficient incremental compilation.
  14. Padalia, Ketan; Fung, Ryan, Method and apparatus for performing efficient incremental compilation.
  15. Borer,Terry; Karchmer,David; Govig,Jason; Leaver,Andrew; Quan,Gabriel; Chan,Kevin; Betz,Vaughn; Brown,Stephen D., Method and apparatus for performing incremental compilation.
  16. Singh,Deshanand P.; Brown,Stephen D., Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays.
  17. Teig, Steven; Hetzel, Asmus, Method and apparatus for performing technology mapping.
  18. Teig, Steven; Hetzel, Asmus, Method and apparatus for performing technology mapping.
  19. Teig, Steven; Hetzel, Asmus, Method and apparatus for performing technology mapping.
  20. Teig,Steven; Hetzel,Asmus, Method and apparatus for performing technology mapping.
  21. Teig, Steven; Hetzel, Asmus, Method and apparatus for pre-tabulating sub-networks.
  22. Teig,Steven; Hetzel,Asmus, Method and apparatus for pre-tabulating sub-networks.
  23. Teig,Steven; Hetzel,Asmus, Method and apparatus for pre-tabulating sub-networks.
  24. Teig, Steven; Hetzel, Asmus, Method and apparatus for producing a circuit description of a design.
  25. Teig, Steven; Hetzel, Asmus, Method and apparatus for producing a circuit description of a design.
  26. Teig, Steven; Caldwell, Andrew, Method and apparatus for routing a set of nets.
  27. Teig,Steven; Hetzel,Asmus, Method and apparatus for specifying encoded sub-networks.
  28. Teig,Steven; Hetzel,Asmus, Method and apparatus for specifying encoded sub-networks.
  29. Teig, Steven; Hetzel, Asmus, Method and apparatus replacing sub-networks within an IC design.
  30. Schiefele, Walter P.; Krueger, Robert O., Method for creating circuit redundancy in programmable logic devices.
  31. Joly Christian ; Dolan Simon, Method for designing application specific integrated circuits.
  32. Fung Fung Lee, Method for incremental timing analysis.
  33. Ginetti, Arnold, Method for updating a placed and routed netlist.
  34. Groeneveld Patrick R. ; van Ginneken Lukas P. P. P., Method of designing a constraint-driven integrated circuit layout.
  35. Yuan,Jinyong; Baeckler,Gregg William; Schleicher, II,James G; Hutton,Michael, Methods of producing application-specific integrated circuit equivalents of programmable logic.
  36. Joly Christian ; Dolan Simon, PLD/ASIC hybrid integrated circuit.
  37. Ochotta,Emil S.; Stiehl,William W.; Shiflet,Eric; Leavesley, III,W. Story, Partition-based incremental implementation flow for use with a programmable logic device.
  38. Fujii,Tetsuya, Peripheral equipment of computer.
  39. Bell, II, William R.; Stiehl, William W.; Ochotta, Emil S.; Leavesley, III, W. Story, Plug-in component-based dependency management for partitions within an incremental implementation flow.
  40. Teig,Steven; Hetzel,Asmus, Structure for storing a plurality of sub-networks.
  41. Wohl Peter ; Anastasakis Demosthenes, System and process of extracting gate-level descriptions from simulation tables for formal verification.
  42. Finn, Simon, Systems and methods for designing an integrated circuit.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로