초록 ▼

A process and a package for achieving wafer scale packaging is described. A layer of a polymeric material, such as polyimide, silicone elastomer, or benzocyclobutene is deposited on the surface of a chip. Via holes through this layer connect to the top surfaces of the studs that pass through the pas

A process and a package for achieving wafer scale packaging is described. A layer of a polymeric material, such as polyimide, silicone elastomer, or benzocyclobutene is deposited on the surface of a chip. Via holes through this layer connect to the top surfaces of the studs that pass through the passivating layer of the chip. In one embodiment, the polymeric layer covers a redistribution network on a previously planarized surface of the chip. Individual chip-level networks are connected together in the kerf so that conductive posts may be formed inside the via holes through electroplating. After the formation of solder bumps, the wafer is diced into individual chips thereby isolating the individual redistribution networks. In a second embodiment, no redistribution network is present so electroless plating is used to form the posts. In a third embodiment, there is also no redistribution network but electroplating is made possible by using a contacting layer. Solder bumps attached to the posts are then formed by means of electroless plating, screen or stencil printing.

대표청구항 ▼

[ What is claimed is:] [1.] A process for wafer scale packaging, comprising:providing a semiconductor wafer, including chip images separated by a kerf area and having a topmost passivating layer through which pass connecting studs;forming a polymeric body having a plurality of metal costs in contact

[ What is claimed is:] [1.] A process for wafer scale packaging, comprising:providing a semiconductor wafer, including chip images separated by a kerf area and having a topmost passivating layer through which pass connecting studs;forming a polymeric body having a plurality of metal costs in contact with, and fixed to, said connecting studs and passing vertically through said polymeric body from said studs; andwherein said posts are of a diameter and height and of a material that they can bend to absorb stress due to thermal mismatch between said semiconductor wafer and said polymeric body.