초록 ▼

A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tables at no extra cost and enable the faster de

A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tables at no extra cost and enable the faster decode of the instruction. The present invention includes the decode of an instruction using an entry ROM, which contains information regarding the instruction that can directly be used in generating the decoder outputs. This information is also used in selecting the correct ROM entry, thus enhancing the flexibility of the decoder, and to dynamically generate a generic microcode entry. Thus, microcode space requirements are reduced. A generic microcode instruction is used for commonly used, similar macroinstructions. This avoids duplication of microcode instructions and thus reduces the required microcode space. The invention also includes the generation of a generic microinstruction dynamically by using the predecoded information selected from the entry microcode table. This makes the generic microinstruction flexible and hence, it can be efficiently be used for many instructions. An entry microcode table, used for the efficient decode of an instruction, contains predecoded information about the instruction apart from the regular microinstruction, which is used directly to generate the decoder outputs and to select the correct microcode entry, and also for the generation of the generic microcode entry. The invention also includes accessing the entry ROM and the .mu.ROM in parallel, using the same address which is generated from the opcode and ModR/M bytes, and selecting one of their outputs. Thus the two ROMs are used efficiently in that the required time and logic are reduced.

대표청구항 ▼

[ What is claimed is:] [11.] An apparatus including a decoder for decoding instructions in a processor and providing a microcode to a sequencer comprising:a buffer for storing an instruction to be decoded and one or more associated operands;an extractor circuit operatively connected to the buffer to

[ What is claimed is:] [11.] An apparatus including a decoder for decoding instructions in a processor and providing a microcode to a sequencer comprising:a buffer for storing an instruction to be decoded and one or more associated operands;an extractor circuit operatively connected to the buffer to read portions of the instruction from the buffer;a first memory operatively connected to the extractor circuit to receive a first plurality of the portions of the instruction and having entries for different instructions and a first plurality of output signals specifyinga microcode bit pattern,a first set of information about the instruction being decoded, andan existence of a primary addressing mode specifier in the instruction;a second memory operatively coupled to the first memory output signal specifying the existence of the primary addressing mode specifier in the instruction and operatively coupled to the extractor circuit in parallel with the first memory, to receive a second plurality of the portions of the instruction, and wherein the second memory includes a second plurality of output signals specifying a second set of information about the instruction and an existence of a secondary addressing mode specifier in the instruction;a third memory operatively connected to the second memory output signal specifying the existence of the secondary addressing mode specifier in the instruction and operatively connected to the extractor circuit in parallel with the first memory and the second memory, to receive a third plurality of the portions of the instruction, and wherein the third memory includes a third plurality of output signals specifying a third set of information about the instruction;a selection logic circuit having an output operatively coupled to a sequencer and a plurality of microcode bit pattern inputs wherein a first microcode bit pattern input is connected to the microcode bit pattern output of the first memory and the selection logic circuit is operative to select one microcode bit pattern from among the plurality of microcode bit pattern inputs;a generic ROM including a bit pattern common to a subset of the instructions and having an output connected to a second microcode bit pattern input of the plurality of microcode bit pattern inputs of the selection logic circuit;a microcode ROM including a microcode for each instruction of the processor and having an output connected to a third microcode bit pattern input of the plurality of microcode bit pattern inputs of the selection logic circuit;a latch register having an output connected to a fourth microcode bit pattern input of the plurality of microcode bit pattern inputs of the selection logic circuit and an input selectively connected to the microcode bit pattern output of the first memory and the output of the microcode ROM wherein the output signal from the first memory specifying the first set of information about the instruction being decoded controls which ofthe microcode bit pattern output of the first memory andthe output of the microcode ROM, is selected; anda size logic circuit for calculating a length of the instruction, having a plurality of inputs operatively connected to the output signals of the first memory, the second memory, and the third memory.