초록 ▼

A semiconductor device structure in which a power semiconductor device is used as the substrate for the structure. Initially, a first metallization layer is formed on the power semiconductor device. Then, a dielectric passivation layer is formed over the first metallization layer, the dielectric pas

A semiconductor device structure in which a power semiconductor device is used as the substrate for the structure. Initially, a first metallization layer is formed on the power semiconductor device. Then, a dielectric passivation layer is formed over the first metallization layer, the dielectric passivation layer having apertures through which the first metallization layer may be accessed. A polymer passivation layer is then formed on the dielectric passivation layer, the polymer passivation layer also having apertures through which the first metallization layer and the dielectric passivation layer may be accessed. A second metallization layer is then formed on the polymer passivation layer to which at least one electronic component is connected. In specific embodiments, the polymer passivation layer includes polyimide.

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor device structure, comprising:a power semiconductor device having a top surface, the power semiconductor device being a substrate for the structure;a first metallization layer deposited over the top surface of the power semiconductor device;a first passivat

[ What is claimed is:] [1.] A semiconductor device structure, comprising:a power semiconductor device having a top surface, the power semiconductor device being a substrate for the structure;a first metallization layer deposited over the top surface of the power semiconductor device;a first passivation layer deposited over the first metallization layer;a second passivation layer deposited over the first passivation layer, the second passivation layer comprising a polymer and having a thickness greater than one micron;a second metallization layer deposited over the second passivation layer; andat least one electronic component disposed above and connected to the second metallization layer; andwherein the polymer has a characteristic capability of withstanding high voltages, the second passivation layer thus providing a selected degree of galvanic isolation between the top surface of the power semiconductor device and the electronic component according to the polymer's capability of withstanding high voltages and the thickness of the second passivation layer.