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Circuitry and methods for internal interconnection of programmable logic devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
  • H01L-025/00
출원번호 US-0086302 (1998-05-28)
발명자 / 주소
  • Reddy Srinivas T.
  • Zaveri Ketan
  • Lane Christopher F.
  • Lee Andy L.
  • McClintock Cameron R.
  • Pedersen Bruce B.
  • Mejia Manuel
  • Cliff Richard G.
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Fish & NeaveTreyz
인용정보 피인용 횟수 : 93  인용 특허 : 41

초록

Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to

대표청구항

[ The invention claimed is:] [1.] A programmable logic device, comprising:a two-dimensional array of intersecting rows and columns of programmable logic super-regions, each of said super-regions including a plurality of programmable logic regions;a plurality of horizontal inter-super-region intercon

이 특허에 인용된 특허 (41)

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  18. Hartmann Robert F. (San Jose CA) Chan Yiu-Fai (Saratoga CA) Frankovich Robert (Cupertino CA) Ou Jung-Hsing (Sunnyvale CA), Programmable logic array device using EPROM technology.
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  32. Costello John C. (San Jose CA) Patel Rakesh H. (Santa Clara CA), Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers.
  33. So Hock-Chuen (Milpitas CA) Wong Sau-Ching (Hillsborough CA), Programmable logic devices with spare circuits for use in replacing defective circuits.
  34. Pedersen Bruce B. (Santa Clara CA) Cliff Richard G. (Santa Clara CA) Ahanin Bahram (Cupertino CA) Lytle Craig S. (Palo Alto CA) Heile Francis B. (Santa Clara CA) Veenstra Kerry S. (Concord CA), Programmable logic element interconnections for programmable logic array integrated circuits.
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  37. Pedersen Bruce B. (Santa Clara CA), Registered logic macrocell with product term allocation and adjacent product term stealing.
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  39. Greene Johathan W. (Palo Alto CA) El Gamal Abbas A. (Palo Alto CA) Kaptanoglu Sinan (San Carlos CA), Segmented routing architecture.
  40. Carter William S. (Santa Clara CA), Special interconnect for configurable logic array.
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