초록 ▼

A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely

A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

대표청구항 ▼

[ I claim:] [1.] A DRAM (dynamic random access memory) cell array supported on a substrate comprising:a plurality of memory cells each having a select-transistor wherein each of said select-transistor having a select-transistor-gate;a peripheral logic-circuit having logic-transistors wherein each of

[ I claim:] [1.] A DRAM (dynamic random access memory) cell array supported on a substrate comprising:a plurality of memory cells each having a select-transistor wherein each of said select-transistor having a select-transistor-gate;a peripheral logic-circuit having logic-transistors wherein each of said logic-transistors having a logic-transistor-gate;said select-transistor-gate and said logic-circuit-gate having substantially a same thickness;said select-transistor for each of said memory cells having a select-transistor threshold voltage and each of said logic-transistors of said peripheral logic-circuit having a logic-transistor threshold voltage wherein said select-transistor threshold voltage is substantially the same as said logic-transistor threshold voltage.