초록 ▼

A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first

A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor integrated circuit device comprising:an integrated circuit chip;an I/O pad formed on said integrated circuit chip;a first insulating film formed on said integrated circuit chip and said I/O pad and having a first opening portion above said I/O pad;a conduc

[ What is claimed is:] [1.] A semiconductor integrated circuit device comprising:an integrated circuit chip;an I/O pad formed on said integrated circuit chip;a first insulating film formed on said integrated circuit chip and said I/O pad and having a first opening portion above said I/O pad;a conductive layer formed on said first insulating film and electrically connected to said I/O pad through the first opening portion;a first barrier metal layer formed on said conductive layer, having substantially the same pattern as that of said conductive layer, and serving to prevent generation of an intermetallic compound by diffusion;a second insulating film formed on said first barrier metal layer, having a planar top surface, and having a second opening portion at a position different from the first opening portion and above said first barrier metal layer;a solder bump formed on said first barrier layer in the second opening portion and not extending onto the planar top surface of the second insulating film,wherein a position of said solder bump is defined by the second opening portion in said second insulating film, anda second barrier metal layer interposed between said solder bump and said first barrier metal layer to prevent .alpha. particles in said solder bump from entering said integrated circuit chip.