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A system and method for receiving direct sequence spread spectrum transmissions with both chip code and frequency uncertainty including a parallel frequency acquisition technique for increasing receiver sensitivity and increasing process gain while reducing a preamble duration required for spread sp

A system and method for receiving direct sequence spread spectrum transmissions with both chip code and frequency uncertainty including a parallel frequency acquisition technique for increasing receiver sensitivity and increasing process gain while reducing a preamble duration required for spread spectrum acquisition. The system and method include techniques for reducing effects of jamming and impulse noise on receiver performance via enhanced antenna diversity by constructively combining received signals. Further, techniques are provided which compensate for chip code alignment drift, providing an associated transmitter maintains carrier and chip code coherence, by comparing received signal energies at varying chip code alignments. These techniques enable the use of lower cost frequency setting crystals in both the receiver and transmitter as well as provide for system operation over a wider temperature range.

대표청구항 ▼

[ What is claimed is:] [63.] A direct sequence spread spectrum system including a transmitter which transmits a spread spectrum signal comprising a direct sequence chip code and a carrier frequency, and a receiver which receives the transmitted signal and resolves carrier frequency uncertainty betwe

[ What is claimed is:] [63.] A direct sequence spread spectrum system including a transmitter which transmits a spread spectrum signal comprising a direct sequence chip code and a carrier frequency, and a receiver which receives the transmitted signal and resolves carrier frequency uncertainty between the carrier frequency of the transmitter and a local reference frequency of the receiver and chip code phase uncertainty between the chip code of the transmitter and a chip code of the receiver, the system comprising:a despreader configured to despread the received signals, comprising a chip code sequence phase shifter which shifts a phase of the receiver chip code sequence while searching to resolve said chip code phase uncertainty;a plurality of filters each having an output of the despreader applied thereto and each having a bandwidth less than said carrier frequency uncertainty; andan operator mechanism configured to detect outputs of said filters at consecutive code chips and to use concurrently detected outputs of the plurality of said filters to determine existence of chip code synchronization at each code chip, and to cause said chip code phase shifter to cease shifting the phase of the receiver chip code when chip code synchronization is determined to exist.