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Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/44
출원번호 US-0024604 (1998-02-17)
발명자 / 주소
  • Dave Bharat P.
  • Jha Niraj K.
  • Lakshminarayana Ganesh
출원인 / 주소
  • Lucent Technologies Inc.
인용정보 피인용 횟수 : 62  인용 특허 : 10

초록

Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present

대표청구항

[ What is claimed is:] [1.] A method for designing the architecture of an embedded system, comprising:(a) a pre-processing phase comprising the steps of:(1) parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded system, wherein the embedded syst

이 특허에 인용된 특허 (10)

  1. Ferguson Edward E. (Plano TX) Cook Dexter S. (Carrollton TX), Critical task scheduling for real-time systems.
  2. Rompaey Karl Van,BEX ; Verkest Diederik,BEX ; Vanhoof Jan,BEX ; Lin Bill,BEX ; Bolsens Ivo,BEX ; De Man Hugo,BEX, Design environment and a design method for hardware/software co-design.
  3. Bayer Nimrod (7 Gordon Street Givataim ILX) Ginosar Ran (Nofit 104 (near Tivon) ILX), High flow-rate synchronizer/scheduler apparatus and method for multiprocessors.
  4. Hunt Peter D. (Pleasanton CA) Elliott Jon K. (Pleasanton CA) Tobias Richard J. (San Jose CA) Herring Alan J. (San Jose CA) Morgan Craig R. (San Jose CA) Hiller John A. (Palo Alto CA), Method for automated deployment of a software program onto a multi-processor architecture.
  5. Austin Edward B. (Woodbridge VA) Robertson Jeffrey E. (Manassas VA), Method for compiling a master task definition data set for defining the logical data flow of a distributed processing ne.
  6. Blelloch Guy E. ; Gibbons Phillip B. ; Matias Yossi, Methods and means for scheduling parallel processors.
  7. Prasanna G.N. Srinivasa, Multiprocessor scheduling and execution.
  8. Kartalopoulos Stamatios V. (Clinton Township ; Hunterdon County NJ), Optimal parallel processor architecture for real time multitasking.
  9. Shafer Stephen Ray ; Ghose Kanad, Parallel program execution time with message consolidation.
  10. Umekita Kazuhiro (Ibaraki JPX) Kametani Masatsugu (Tsuchiura JPX), Program parallelizing apparatus capable of optimizing processing time.

이 특허를 인용한 특허 (62)

  1. Honary, Hooman; Chen, Inching; Tsui, Ernest T., Allocation of combined or separate data and control planes.
  2. Honary,Hooman; Chen,Inching; Tsui,Ernest T., Allocation of combined or separate data and control planes.
  3. Loomis, Stephen; Gondhalekar, Mangesh Madhukar, Apparatus and method for skipping songs without delay.
  4. Yoshimura, Hideyoshi, Asymmetrical multiprocessor system, image processing apparatus and image forming apparatus using same, and unit job processing method using asymmetrical multiprocessor.
  5. Phan Vogel, Dieu Q., Automated method and apparatus for very early validation of chip power distribution networks in semiconductor chip designs.
  6. Klein,Russell Alan, Automated repartitioning of hardware and software components in an embedded system.
  7. Lin, Kuoching; Liu, Lungtien, Clustering circuit paths in electronic circuit design.
  8. Lin,Kuoching; Liu,Lungtien, Clustering circuit paths in electronic circuit design.
  9. Tsai,Vicki W.; Honary,Hooman; Tsui,Ernest T., Constraints-directed compilation for heterogeneous reconfigurable architectures.
  10. May,Philip E.; Lucas,Brian G.; Moat,Kent D., Dataflow graph compression for power reduction in a vector processor.
  11. Verosub,Ellis; Tenneti,Sanjeev; Acharya,Kamal; Goldfarb,Solomon D.; Pringle,Todd; Bill,David S.; Prakash,Shailesh; Milligan,Adam, Digital content store system.
  12. Ito,Takafumi, Distributed control method and apparatus.
  13. Mizrachi, Shay; Tal, Uri; Ben-David, Tomer; Geller, Ishay; Kasher, Ido; Gal, Ronen, Efficient parallel computation of dependency problems.
  14. Chauvel, Gerard; D'Inverno, Dominique; Lasserre, Serge; Kuusela, Maija; Cabillic, Gilbert; Lesot, Jean-Philippe; Banâtre, Michel; Parain, Frédéric; Routeau, Jean-Paul; Majoul, Salam, Energy-aware scheduling of application execution.
  15. Robert S. Schreiber, Function unit allocation in processor design.
  16. Subbu Ganesan ; Leonid Alexander Broukhis ; Ramesh Narayanaswamy ; Ian Michael Nixon, Functional verification of both cycle-based and non-cycle based designs.
  17. Ganesan, Subbu; Pillalamarri, Shyam Prasad, Functional verification of integrated circuit designs.
  18. Ganesan, Subbu; Broukhis, Leonid Alexander; Narayanaswamy, Ramesh; Nixon, Ian Michael, Functional verification system.
  19. Dave Bharat P. ; Jha Niraj K., Hardware-software co-synthesis of hierarchical heterogeneous distributed embedded systems.
  20. Dave, Bharat P., Hardware/software co-synthesis of heterogeneous low-power and fault-tolerant systems-on-a chip.
  21. Prasanna, Deepak; Fudge, Gerald L., Heterogeneous reconfigurable agent compute engine (HRACE).
  22. Yamasaki, Kenta; Iizuka, Daisuke; Kudo, Yutaka, Job scheduling apparatus and method based on island execution time.
  23. Norris,James M.; May,Philip E.; Moat,Kent D.; Essick, IV,Raymond B.; Lucas,Brian G., Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values.
  24. May,Philip E.; Essick, IV,Raymond B.; Lucas,Brian G.; Moat,Kent D.; Norris,James M., Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters.
  25. Floyd,Michael Stephen; Friedrich,Joshua David; Huston,Elspeth Anne; Roesner,Wolfgang; Weiss,Rick John, Method and apparatus for specifying multiple voltage domains and validating physical implementation and interconnections in a processor chip.
  26. Norman, David Everton, Method and system for splitting scheduling problems into sub-problems.
  27. Thabet, Farhat; Ben Chehida, Karim; Blanc, Frédérique, Method for managing energy consumption for multiprocessor systems using an offline phase for characterization of a variation of a potential rate of parallelism for task scheduling and an online phase for detection and exploitation of potential inactivity intervals.
  28. Jain,Rajiv; Su,Alan Peisheng; Biswas,Chaitali, Method for modeling and processing asynchronous functional specification for system level architecture synthesis.
  29. Zammit,Vincent; Kay,Andrew, Method of co-simulating a digital circuit.
  30. Raghunathan, Anand; Lakshminarayana, Ganesh; Lahiri, Kanishka; Dey, Sujit, Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners.
  31. Beatty, III, Harry J.; Elmendorf, Peter C.; Gates, Charles; Luo, Chen, Methods and systems for delegating work objects across a mixed computer environment.
  32. Beatty, III, Harry J.; Elmendorf, Peter C.; Gates, Charles; Luo, Chen, Methods and systems for linking objects across a mixed computer environment.
  33. Gondhalekar,Mangesh Madhukar; Viswanathan,Rajesh; Prakash,Shailesh; Loomis,Stephen; Van Huysse,James Patrick; Carlson,Cameo Dawn, Multimedia scheduler.
  34. Schmidt, Jeffrey S.; Jenkinson, Mark E., Operating system and architecture for embedded system.
  35. Schmidt, Jeffrey S.; Jenkinson, Mark E., Operating system and architecture for embedded system.
  36. Tessier, Russell George; Betz, Vaughn Timothy; Golpalsamy, Thiagaraja; Neto, David, Power-aware RAM processing.
  37. Hoang, Khoi, Prefetched data in a digital broadcast system.
  38. MacInnis, Alexander, Real time scheduling system for operating system.
  39. Moona, Rajat; Klein, Russell Alan, Repartitioning performance estimation in a hardware-software system.
  40. Liu, Jie; Zhao, Feng; Goraczko, Michel; Matic, Slobodan; Lymberopoulos, Dimitrios; Priyantha, Nissanka, Resource modeling and scheduling for extensible computing platforms.
  41. Ganesan, Subbu; Broukhis, Leonid Alexander; Narayanaswamy, Ramesh; Nixon, Ian Michael, Run-time controller in a functional verification system.
  42. May,Philip E.; Moat,Kent Donald; Essick, IV,Raymond B.; Chiricescu,Silviu; Lucas,Brian Geoffrey; Norris,James M.; Schuette,Michael Allen; Saidi,Ali, Scheduler of program instructions for streaming vector processor having interconnected functional units.
  43. Veditz,Daniel P., Self-contained applications that are applied to be received by and processed within a browser environment and that have a first package that includes a manifest file and an archive of files including a markup language file and second package.
  44. Vakada,Sridhar; Schulz,Jurgen M., Static scheduling of test cases.
  45. Lucas,Brian Geoffrey; May,Philip E.; Moat,Kent Donald; Essick, IV,Raymond B.; Chiricescu,Silviu; Norris,James M.; Schuette,Michael Allen; Saidi,Ali, Streaming vector processor with reconfigurable interconnection switch.
  46. Shpigelman, Igor, Support of non-trivial scheduling policies along with topological properties.
  47. Shpigelman, Igor, Support of non-trivial scheduling policies along with topological properties.
  48. Neiman, Steven; Sulzhyk, Roman, System and method for allocating computing resources of a distributed computing system.
  49. Cousins, David Bruce; Daily, Matthew Paul; Lirakis, Christopher Burbank, System and method for automatically optimizing heterogenous multiprocessor software performance.
  50. Neiman, Steven; Sulzhyk, Roman, System and method for caching results.
  51. Neiman,Steven; Sulzhyk,Roman, System and method for caching results.
  52. Neiman,Steven; Sulzhyk,Roman, System and method for dividing computations.
  53. Neiman,Steven; Sulzhyk,Roman, System and method for dividing computations.
  54. Mankovski, Serguei, System and method for managing, scheduling, controlling and monitoring execution of jobs by a job scheduler utilizing a publish/subscription interface.
  55. Mankovskii, Serguei; Banger, Colin; Steele, Jody; Gray, Tomas, System and method for modifying execution of scripts for a job scheduler using deontic logic.
  56. Neiman,Steven; Sulzhyk,Roman, System architecture for distributed computing and method of using the system.
  57. Neiman, Steven; Sulzhyk, Roman, System for allocating computing resources of distributed computer system with transaction manager.
  58. Shimomura, Munehiro, System for session management of resources and tasks having records in the lookup table for the session.
  59. Dorofeev,Andrei V.; Tucker,Andrew G., System using fair-share scheduling technique to schedule processes within each processor set based on the number of shares assigned to each process group.
  60. Abe,Atsushi; Miyamura,Tsuyoshi, System, method, and program for controlling execution sequencing of multiple jobs.
  61. Hoang, Khoi, Systems and methods for providing video-on-demand services for broadcasting systems.
  62. Ganesan, Subbu; Broukhis, Leonid Alexander; Narayanaswamy, Ramesh; Nixon, Ian Michael, Tracing the change of state of a signal in a functional verification system.
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