Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/44
출원번호
US-0024604
(1998-02-17)
발명자
/ 주소
Dave Bharat P.
Jha Niraj K.
Lakshminarayana Ganesh
출원인 / 주소
Lucent Technologies Inc.
인용정보
피인용 횟수 :
62인용 특허 :
10
초록▼
Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present
Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.), 2) it supports both concurrent and sequential modes of communication and computation, 3) it employs a combination of preemptive and non-preemptive scheduling, 4) it introduces the concept of an association array to tackle the problem of multi-rate systems (which are commonly found in multimedia applications), 5) it uses a static scheduler based on deadline-based priority levels for accurate performance estimation of a co-synthesis solution, 6) it uses a new task clustering technique which takes the changing nature of the critical path in the task graph into account, 7) it supports pipelining of task graphs to derive a cost-efficient architecture, 8) it supports a mix of various technologies, such as 5 V CMOS, 3.3 V CMOS, 2.7 V CMOS, ECL, etc., to meet embedded system constraints and minimize power dissipation, and 9) if desired, it also optimizes the architecture for power consumption.
대표청구항▼
[ What is claimed is:] [1.] A method for designing the architecture of an embedded system, comprising:(a) a pre-processing phase comprising the steps of:(1) parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded system, wherein the embedded syst
[ What is claimed is:] [1.] A method for designing the architecture of an embedded system, comprising:(a) a pre-processing phase comprising the steps of:(1) parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded system, wherein the embedded system has two or more instances of at least one task graph; and(2) generating an association array for the task graphs, wherein the association array stores a limited amount of information for each instance of a task graph of the embedded system to avoid replication of a full description for each task graph having two or more instances and its associated parameters; and(b) a synthesis phase, following the pre-processing phase, comprising the step of allocating one or more groups of one or more tasks in the tasks graphs to one or more processing elements (PEs) in the resource library and allocating one or more edges in the tasks graphs to one or more communication links in the resource library, based on performance evaluation of one or more possible allocations for each of the groups and edges in light of the system/task constraints, wherein the performance evaluation uses the association array.
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이 특허에 인용된 특허 (10)
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Veditz,Daniel P., Self-contained applications that are applied to be received by and processed within a browser environment and that have a first package that includes a manifest file and an archive of files including a markup language file and second package.
Cousins, David Bruce; Daily, Matthew Paul; Lirakis, Christopher Burbank, System and method for automatically optimizing heterogenous multiprocessor software performance.
Mankovski, Serguei, System and method for managing, scheduling, controlling and monitoring execution of jobs by a job scheduler utilizing a publish/subscription interface.
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Dorofeev,Andrei V.; Tucker,Andrew G., System using fair-share scheduling technique to schedule processes within each processor set based on the number of shares assigned to each process group.
Ganesan, Subbu; Broukhis, Leonid Alexander; Narayanaswamy, Ramesh; Nixon, Ian Michael, Tracing the change of state of a signal in a functional verification system.
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